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authorGravatar Kishon Vijay Abraham I <kishon@ti.com> 2021-06-03 19:52:49 +0530
committerGravatar Nishanth Menon <nm@ti.com> 2021-06-08 09:32:38 -0500
commit354065bed2d15f6ff7796c8105133ccdf3a84917 (patch)
tree8da2467e1de8316dcfb18d53e16951d13986e738 /arch/arm64/boot/dts/ti/k3-am642-evm.dts
parentarm64: dts: ti: k3-am64-main: Add PCIe DT node (diff)
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arm64: dts: ti: k3-am642-evm: Enable PCIe and SERDES
AM642 EVM has a x4 lane PCIe connector. Enable PCIe in RC mode here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210603142251.14563-4-kishon@ti.com
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-am642-evm.dts')
-rw-r--r--arch/arm64/boot/dts/ti/k3-am642-evm.dts30
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index dad0efa961ed..8c27f563a390 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -5,6 +5,8 @@
/dts-v1/;
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
@@ -466,3 +468,31 @@
&mailbox0_cluster7 {
status = "disabled";
};
+
+&serdes_ln_ctrl {
+ idle-states = <AM64_SERDES0_LANE0_PCIE0>;
+};
+
+&serdes0 {
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&pcie0_rc {
+ reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
+&pcie0_ep {
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+ status = "disabled";
+};