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author | 2020-08-02 22:23:56 +0530 | |
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committer | 2020-08-31 06:31:24 -0500 | |
commit | 269a5641b1ed0ac00e9d75b43985407b34540d77 (patch) | |
tree | ec572e449ce60dd1b2abb49ddd5c1104659ea6f7 /arch/arm64/boot/dts/ti/k3-am65-main.dtsi | |
parent | arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores (diff) | |
download | linux-269a5641b1ed0ac00e9d75b43985407b34540d77.tar.gz linux-269a5641b1ed0ac00e9d75b43985407b34540d77.tar.bz2 linux-269a5641b1ed0ac00e9d75b43985407b34540d77.zip |
arm64: dts: ti: k3-am65: restrict PCIe to Gen2 speed
Per errata i2104 documented in AM65x device errata document (TI document
number SPRZ452E, revised June 2019), Gen3 operation is not supported for
both PCIe Root Complex and Endpoint modes of operation.
See: https://www.ti.com/lit/er/sprz452e/sprz452e.pdf
Restrict speed to Gen2 to address the errata.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20200802165356.10285-1-nsekhar@ti.com
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-am65-main.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index e12759ce7918..76e0edc4ad5c 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -704,7 +704,7 @@ ti,syscon-pcie-mode = <&pcie0_mode>; bus-range = <0x0 0xff>; num-viewport = <16>; - max-link-speed = <3>; + max-link-speed = <2>; dma-coherent; interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; msi-map = <0x0 &gic_its 0x0 0x10000>; @@ -718,7 +718,7 @@ ti,syscon-pcie-mode = <&pcie0_mode>; num-ib-windows = <16>; num-ob-windows = <16>; - max-link-speed = <3>; + max-link-speed = <2>; dma-coherent; interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; }; @@ -736,7 +736,7 @@ ti,syscon-pcie-mode = <&pcie1_mode>; bus-range = <0x0 0xff>; num-viewport = <16>; - max-link-speed = <3>; + max-link-speed = <2>; dma-coherent; interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; msi-map = <0x0 &gic_its 0x10000 0x10000>; @@ -750,7 +750,7 @@ ti,syscon-pcie-mode = <&pcie1_mode>; num-ib-windows = <16>; num-ob-windows = <16>; - max-link-speed = <3>; + max-link-speed = <2>; dma-coherent; interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; }; |