diff options
| author |  Pratyush Yadav <p.yadav@ti.com>
| 2021-03-05 21:09:26 +0530 |
|---|---|---|
| committer |  Nishanth Menon <nm@ti.com>
| 2021-03-11 08:12:45 -0600 |
| commit | efbdf2e9183bd5e75c64d251c6b673ca61ea01b3 (patch) | |
| tree | c835139ab1c1ff745b6489e0815b1c03802f6431 /arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | |
| parent | arm64: dts: ti: am654-base-board: Enable 8D-8D-8D mode on OSPI (diff) | |
| download | linux-efbdf2e9183bd5e75c64d251c6b673ca61ea01b3.tar.gz linux-efbdf2e9183bd5e75c64d251c6b673ca61ea01b3.tar.bz2 linux-efbdf2e9183bd5e75c64d251c6b673ca61ea01b3.zip | |
arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0
TI J7200 has the Cadence OSPI controller for interfacing with OSPI
flashes. Add its node to allow using SPI flashes.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20210305153926.3479-4-p.yadav@ti.com
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 359e3e8a8cd0..5408ec815d58 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -269,6 +269,23 @@ #size-cells = <1>; mux-controls = <&hbmc_mux 0>; }; + + ospi0: spi@47040000 { + compatible = "ti,am654-ospi"; + reg = <0x0 0x47040000 0x0 0x100>, + <0x5 0x00000000 0x1 0x0000000>; + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 103 0>; + assigned-clocks = <&k3_clks 103 0>; + assigned-clock-parents = <&k3_clks 103 2>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + }; }; tscadc0: tscadc@40200000 { |