diff options
Diffstat (limited to 'drivers/net/wireless/realtek/rtw89/mac.h')
| -rw-r--r-- | drivers/net/wireless/realtek/rtw89/mac.h | 243 |
1 files changed, 223 insertions, 20 deletions
diff --git a/drivers/net/wireless/realtek/rtw89/mac.h b/drivers/net/wireless/realtek/rtw89/mac.h index c11c904f87fe..6fb457153a11 100644 --- a/drivers/net/wireless/realtek/rtw89/mac.h +++ b/drivers/net/wireless/realtek/rtw89/mac.h @@ -10,6 +10,7 @@ #define MAC_MEM_DUMP_PAGE_SIZE 0x40000 #define ADDR_CAM_ENT_SIZE 0x40 +#define ADDR_CAM_ENT_SHORT_SIZE 0x20 #define BSSID_CAM_ENT_SIZE 0x08 #define HFC_PAGE_UNIT 64 #define RPWM_TRY_CNT 3 @@ -168,6 +169,12 @@ enum rtw89_mac_ax_l0_to_l1_event { MAC_AX_L0_TO_L1_EVENT_MAX = 15, }; +enum rtw89_mac_wow_fw_status { + WOWLAN_NOT_READY = 0x00, + WOWLAN_SLEEP_READY = 0x01, + WOWLAN_RESUME_READY = 0x02, +}; + #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32) enum rtw89_mac_dbg_port_sel { @@ -405,13 +412,21 @@ enum rtw89_mac_c2h_mcc_func { NUM_OF_RTW89_MAC_C2H_FUNC_MCC, }; +enum rtw89_mac_c2h_mrc_func { + RTW89_MAC_C2H_FUNC_MRC_TSF_RPT = 0, + RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT = 1, + + NUM_OF_RTW89_MAC_C2H_FUNC_MRC, +}; + enum rtw89_mac_c2h_class { - RTW89_MAC_C2H_CLASS_INFO, - RTW89_MAC_C2H_CLASS_OFLD, - RTW89_MAC_C2H_CLASS_TWT, - RTW89_MAC_C2H_CLASS_WOW, - RTW89_MAC_C2H_CLASS_MCC, - RTW89_MAC_C2H_CLASS_FWDBG, + RTW89_MAC_C2H_CLASS_INFO = 0x0, + RTW89_MAC_C2H_CLASS_OFLD = 0x1, + RTW89_MAC_C2H_CLASS_TWT = 0x2, + RTW89_MAC_C2H_CLASS_WOW = 0x3, + RTW89_MAC_C2H_CLASS_MCC = 0x4, + RTW89_MAC_C2H_CLASS_FWDBG = 0x5, + RTW89_MAC_C2H_CLASS_MRC = 0xe, RTW89_MAC_C2H_CLASS_MAX, }; @@ -440,6 +455,12 @@ enum rtw89_mac_mcc_status { RTW89_MAC_MCC_TXNULL1_FAIL = 27, }; +enum rtw89_mac_mrc_status { + RTW89_MAC_MRC_START_SCH_OK = 0, + RTW89_MAC_MRC_STOP_SCH_OK = 1, + RTW89_MAC_MRC_DEL_SCH_OK = 2, +}; + struct rtw89_mac_ax_coex { #define RTW89_MAC_AX_COEX_RTK_MODE 0 #define RTW89_MAC_AX_COEX_CSR_MODE 1 @@ -536,6 +557,9 @@ enum rtw89_mac_bf_rrsc_rate { #define B_CMAC1_MGQ_NO_PWRSAV BIT(11) #define B_CMAC1_CPUMGQ BIT(12) +#define B_CMAC0_MGQ_NORMAL_BE BIT(2) +#define B_CMAC1_MGQ_NORMAL_BE BIT(30) + #define QEMP_ACQ_GRP_MACID_NUM 8 #define QEMP_ACQ_GRP_QSEL_SH 4 #define QEMP_ACQ_GRP_QSEL_MASK 0xF @@ -649,6 +673,22 @@ struct rtw89_mac_dle_dfi_qempty { u32 qempty; }; +enum rtw89_mac_dle_rsvd_qt_type { + DLE_RSVD_QT_MPDU_INFO, + DLE_RSVD_QT_B0_CSI, + DLE_RSVD_QT_B1_CSI, + DLE_RSVD_QT_B0_LMR, + DLE_RSVD_QT_B1_LMR, + DLE_RSVD_QT_B0_FTM, + DLE_RSVD_QT_B1_FTM, +}; + +struct rtw89_mac_dle_rsvd_qt_cfg { + u16 pktid; + u16 pg_num; + u32 size; +}; + enum rtw89_mac_error_scenario { RTW89_RXI300_ERROR = 1, RTW89_WCPU_CPU_EXCEPTION = 2, @@ -817,27 +857,37 @@ enum mac_ax_err_info { struct rtw89_mac_size_set { const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie; + const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c0; + const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c2; const struct rtw89_dle_size wde_size0; + const struct rtw89_dle_size wde_size0_v1; const struct rtw89_dle_size wde_size4; + const struct rtw89_dle_size wde_size4_v1; const struct rtw89_dle_size wde_size6; const struct rtw89_dle_size wde_size7; const struct rtw89_dle_size wde_size9; const struct rtw89_dle_size wde_size18; const struct rtw89_dle_size wde_size19; const struct rtw89_dle_size ple_size0; + const struct rtw89_dle_size ple_size0_v1; + const struct rtw89_dle_size ple_size3_v1; const struct rtw89_dle_size ple_size4; const struct rtw89_dle_size ple_size6; const struct rtw89_dle_size ple_size8; const struct rtw89_dle_size ple_size18; const struct rtw89_dle_size ple_size19; const struct rtw89_wde_quota wde_qt0; + const struct rtw89_wde_quota wde_qt0_v1; const struct rtw89_wde_quota wde_qt4; const struct rtw89_wde_quota wde_qt6; const struct rtw89_wde_quota wde_qt7; const struct rtw89_wde_quota wde_qt17; const struct rtw89_wde_quota wde_qt18; + const struct rtw89_ple_quota ple_qt0; + const struct rtw89_ple_quota ple_qt1; const struct rtw89_ple_quota ple_qt4; const struct rtw89_ple_quota ple_qt5; + const struct rtw89_ple_quota ple_qt9; const struct rtw89_ple_quota ple_qt13; const struct rtw89_ple_quota ple_qt18; const struct rtw89_ple_quota ple_qt44; @@ -848,6 +898,10 @@ struct rtw89_mac_size_set { const struct rtw89_ple_quota ple_qt_52a_wow; const struct rtw89_ple_quota ple_qt_52b_wow; const struct rtw89_ple_quota ple_qt_51b_wow; + const struct rtw89_rsvd_quota ple_rsvd_qt0; + const struct rtw89_rsvd_quota ple_rsvd_qt1; + const struct rtw89_dle_rsvd_size rsvd0_size0; + const struct rtw89_dle_rsvd_size rsvd1_size0; }; extern const struct rtw89_mac_size_set rtw89_mac_size; @@ -860,22 +914,80 @@ struct rtw89_mac_gen_def { u32 rx_fltr; const struct rtw89_port_reg *port_base; u32 agg_len_ht; + u32 ps_status; struct rtw89_reg_def muedca_ctrl; struct rtw89_reg_def bfee_ctrl; - + struct rtw89_reg_def narrow_bw_ru_dis; + struct rtw89_reg_def wow_ctrl; + + int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band, + enum rtw89_mac_hwmod_sel sel); + int (*sys_init)(struct rtw89_dev *rtwdev); + int (*trx_init)(struct rtw89_dev *rtwdev); + void (*hci_func_en)(struct rtw89_dev *rtwdev); + void (*dmac_func_pre_en)(struct rtw89_dev *rtwdev); + void (*dle_func_en)(struct rtw89_dev *rtwdev, bool enable); + void (*dle_clk_en)(struct rtw89_dev *rtwdev, bool enable); void (*bf_assoc)(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_sta *sta); + int (*typ_fltr_opt)(struct rtw89_dev *rtwdev, + enum rtw89_machdr_frame_type type, + enum rtw89_mac_fwd_target fwd_target, + u8 mac_idx); + int (*cfg_ppdu_status)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable); + + int (*dle_mix_cfg)(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg); + int (*chk_dle_rdy)(struct rtw89_dev *rtwdev, bool wde_or_ple); + int (*dle_buf_req)(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id); + void (*hfc_func_en)(struct rtw89_dev *rtwdev, bool en, bool h2c_en); + void (*hfc_h2c_cfg)(struct rtw89_dev *rtwdev); + void (*hfc_mix_cfg)(struct rtw89_dev *rtwdev); + void (*hfc_get_mix_info)(struct rtw89_dev *rtwdev); + void (*wde_quota_cfg)(struct rtw89_dev *rtwdev, + const struct rtw89_wde_quota *min_cfg, + const struct rtw89_wde_quota *max_cfg, + u16 ext_wde_min_qt_wcpu); + void (*ple_quota_cfg)(struct rtw89_dev *rtwdev, + const struct rtw89_ple_quota *min_cfg, + const struct rtw89_ple_quota *max_cfg); + int (*set_cpuio)(struct rtw89_dev *rtwdev, + struct rtw89_cpuio_ctrl *ctrl_para, bool wd); + int (*dle_quota_change)(struct rtw89_dev *rtwdev, bool band1_en); + void (*disable_cpu)(struct rtw89_dev *rtwdev); int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw, bool include_bb); u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type); int (*fwdl_check_path_ready)(struct rtw89_dev *rtwdev, bool h2c_or_fwdl); + int (*parse_efuse_map)(struct rtw89_dev *rtwdev); + int (*parse_phycap_map)(struct rtw89_dev *rtwdev); + int (*cnv_efuse_state)(struct rtw89_dev *rtwdev, bool idle); + + int (*cfg_plt)(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); + u16 (*get_plt_cnt)(struct rtw89_dev *rtwdev, u8 band); bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u32 reg_base, u32 *cr); + + int (*write_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask); + int (*read_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 *val); + + void (*dump_qta_lost)(struct rtw89_dev *rtwdev); + void (*dump_err_status)(struct rtw89_dev *rtwdev, + enum mac_ax_err_info err); + + bool (*is_txq_empty)(struct rtw89_dev *rtwdev); + + int (*add_chan_list)(struct rtw89_dev *rtwdev, + struct rtw89_vif *rtwvif, bool connected); + int (*scan_offload)(struct rtw89_dev *rtwdev, + struct rtw89_scan_option *option, + struct rtw89_vif *rtwvif); + + int (*wow_config_mac)(struct rtw89_dev *rtwdev, bool enable_wow); }; extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax; @@ -977,10 +1089,31 @@ rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev); int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb); int rtw89_mac_init(struct rtw89_dev *rtwdev); +int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, + enum rtw89_qta_mode ext_mode); +int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en); +int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, + enum rtw89_qta_mode mode); +bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode); +static inline int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, - enum rtw89_mac_hwmod_sel sel); + enum rtw89_mac_hwmod_sel sel) +{ + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; + + return mac->check_mac_en(rtwdev, band, sel); +} + int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); +int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl); +int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, + struct rtw89_mac_dle_dfi_quota *quota); +void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev); +int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, + struct rtw89_mac_dle_dfi_qempty *qempty); +void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, + enum mac_ax_err_info err); int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, @@ -989,9 +1122,12 @@ void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, u16 offset_tu); int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u64 *tsf); +void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, + struct rtw89_vif *rtwvif, bool en); void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); +void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en); int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev); int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev); @@ -1010,9 +1146,27 @@ static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev) return chip->ops->disable_bb_rf(rtwdev); } +static inline int rtw89_chip_reset_bb_rf(struct rtw89_dev *rtwdev) +{ + int ret; + + if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) + return 0; + + ret = rtw89_chip_disable_bb_rf(rtwdev); + if (ret) + return ret; + ret = rtw89_chip_enable_bb_rf(rtwdev); + if (ret) + return ret; + + return 0; +} + u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev); int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err); -bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func); +bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, + u8 class, u8 func); void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len, u8 class, u8 func); int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev); @@ -1020,9 +1174,20 @@ int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 *tx_en, enum rtw89_sch_tx_sel sel); int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 *tx_en, enum rtw89_sch_tx_sel sel); +int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, + u32 *tx_en, enum rtw89_sch_tx_sel sel); int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); -int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_ids, bool enable); +int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); + +static inline +int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) +{ + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; + + return mac->cfg_ppdu_status(rtwdev, mac_idx, enable); +} + void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx); void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop); int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); @@ -1032,13 +1197,31 @@ int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex_gnt *gnt_cfg); int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex_gnt *gnt_cfg); -int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); -u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band); +int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev, + const struct rtw89_mac_ax_coex_gnt *gnt_cfg); + +static inline +int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) +{ + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; + + return mac->cfg_plt(rtwdev, plt); +} + +static inline +u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) +{ + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; + + return mac->get_plt_cnt(rtwdev, band); +} + void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl); +int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl); void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev); @@ -1185,15 +1368,19 @@ enum rtw89_mac_xtal_si_offset { #define XTAL_SC_XI_MASK GENMASK(7, 0) XTAL_SI_XTAL_SC_XO = 0x05, #define XTAL_SC_XO_MASK GENMASK(7, 0) + XTAL_SI_XREF_MODE = 0x0B, XTAL_SI_PWR_CUT = 0x10, #define XTAL_SI_SMALL_PWR_CUT BIT(0) #define XTAL_SI_BIG_PWR_CUT BIT(1) XTAL_SI_XTAL_DRV = 0x15, #define XTAL_SI_DRV_LATCH BIT(4) + XTAL_SI_XTAL_PLL = 0x16, XTAL_SI_XTAL_XMD_2 = 0x24, #define XTAL_SI_LDO_LPS GENMASK(6, 4) XTAL_SI_XTAL_XMD_4 = 0x26, #define XTAL_SI_LPS_CAP GENMASK(3, 0) + XTAL_SI_XREF_RF1 = 0x2D, + XTAL_SI_XREF_RF2 = 0x2E, XTAL_SI_CV = 0x41, #define XTAL_SI_ACV_MASK GENMASK(3, 0) XTAL_SI_LOW_ADDR = 0x62, @@ -1221,20 +1408,36 @@ enum rtw89_mac_xtal_si_offset { XTAL_SI_SRAM_CTRL = 0xA1, #define XTAL_SI_SRAM_DIS BIT(1) #define FULL_BIT_MASK GENMASK(7, 0) + XTAL_SI_APBT = 0xD1, + XTAL_SI_PLL = 0xE0, + XTAL_SI_PLL_1 = 0xE1, }; -int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask); -int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val); +static inline +int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) +{ + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; + + return mac->write_xtal_si(rtwdev, offset, val, mask); +} + +static inline +int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) +{ + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; + + return mac->read_xtal_si(rtwdev, offset, val); +} + void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); -int rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id); -int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, - struct rtw89_cpuio_ctrl *ctrl_para, bool wd); -int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, - enum rtw89_machdr_frame_type type, - enum rtw89_mac_fwd_target fwd_target, u8 mac_idx); int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow); int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, enum rtw89_mac_idx band); void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow); +int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, + bool band1_en); +int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, + enum rtw89_mac_dle_rsvd_qt_type type, + struct rtw89_mac_dle_rsvd_qt_cfg *cfg); #endif |