diff options
Diffstat (limited to 'include/sound')
48 files changed, 2995 insertions, 699 deletions
diff --git a/include/sound/ac97_codec.h b/include/sound/ac97_codec.h index 49200ec26dc4..c495c6d5fbe0 100644 --- a/include/sound/ac97_codec.h +++ b/include/sound/ac97_codec.h @@ -335,6 +335,9 @@ static inline int snd_ac97_update_power(struct snd_ac97 *ac97, int reg, #ifdef CONFIG_PM void snd_ac97_suspend(struct snd_ac97 *ac97); void snd_ac97_resume(struct snd_ac97 *ac97); +#else +static inline void snd_ac97_suspend(struct snd_ac97 *ac97) {} +static inline void snd_ac97_resume(struct snd_ac97 *ac97) {} #endif int snd_ac97_reset(struct snd_ac97 *ac97, bool try_warm, unsigned int id, unsigned int id_mask); diff --git a/include/sound/asequencer.h b/include/sound/asequencer.h index 18d4bc3ee0b7..ddbb6bf801bb 100644 --- a/include/sound/asequencer.h +++ b/include/sound/asequencer.h @@ -65,6 +65,10 @@ #define snd_seq_ev_is_abstime(ev) (snd_seq_ev_timemode_type(ev) == SNDRV_SEQ_TIME_MODE_ABS) #define snd_seq_ev_is_reltime(ev) (snd_seq_ev_timemode_type(ev) == SNDRV_SEQ_TIME_MODE_REL) +/* check whether the given event is a UMP event */ +#define snd_seq_ev_is_ump(ev) \ + (IS_ENABLED(CONFIG_SND_SEQ_UMP) && ((ev)->flags & SNDRV_SEQ_EVENT_UMP)) + /* queue sync port */ #define snd_seq_queue_sync_port(q) ((q) + 16) diff --git a/include/sound/compress_driver.h b/include/sound/compress_driver.h index d91289c6f00e..bcf872c17dd3 100644 --- a/include/sound/compress_driver.h +++ b/include/sound/compress_driver.h @@ -148,7 +148,7 @@ struct snd_compr_ops { */ struct snd_compr { const char *name; - struct device dev; + struct device *dev; struct snd_compr_ops *ops; void *private_data; struct snd_card *card; diff --git a/include/sound/control.h b/include/sound/control.h index cc3dcc6cfb0f..9a4f4f7138da 100644 --- a/include/sound/control.h +++ b/include/sound/control.h @@ -140,8 +140,32 @@ int snd_ctl_remove_id(struct snd_card * card, struct snd_ctl_elem_id *id); int snd_ctl_rename_id(struct snd_card * card, struct snd_ctl_elem_id *src_id, struct snd_ctl_elem_id *dst_id); void snd_ctl_rename(struct snd_card *card, struct snd_kcontrol *kctl, const char *name); int snd_ctl_activate_id(struct snd_card *card, struct snd_ctl_elem_id *id, int active); -struct snd_kcontrol *snd_ctl_find_numid(struct snd_card * card, unsigned int numid); -struct snd_kcontrol *snd_ctl_find_id(struct snd_card * card, struct snd_ctl_elem_id *id); +struct snd_kcontrol *snd_ctl_find_numid_locked(struct snd_card *card, unsigned int numid); +struct snd_kcontrol *snd_ctl_find_numid(struct snd_card *card, unsigned int numid); +struct snd_kcontrol *snd_ctl_find_id_locked(struct snd_card *card, const struct snd_ctl_elem_id *id); +struct snd_kcontrol *snd_ctl_find_id(struct snd_card *card, const struct snd_ctl_elem_id *id); + +/** + * snd_ctl_find_id_mixer - find the control instance with the given name string + * @card: the card instance + * @name: the name string + * + * Finds the control instance with the given name and + * @SNDRV_CTL_ELEM_IFACE_MIXER. Other fields are set to zero. + * + * This is merely a wrapper to snd_ctl_find_id(). + * + * Return: The pointer of the instance if found, or %NULL if not. + */ +static inline struct snd_kcontrol * +snd_ctl_find_id_mixer(struct snd_card *card, const char *name) +{ + struct snd_ctl_elem_id id = {}; + + id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; + strscpy(id.name, name, sizeof(id.name)); + return snd_ctl_find_id(card, &id); +} int snd_ctl_create(struct snd_card *card); @@ -238,6 +262,9 @@ snd_ctl_add_follower(struct snd_kcontrol *master, struct snd_kcontrol *follower) return _snd_ctl_add_follower(master, follower, 0); } +int snd_ctl_add_followers(struct snd_card *card, struct snd_kcontrol *master, + const char * const *list); + /** * snd_ctl_add_follower_uncached - Add a virtual follower control * @master: vmaster element diff --git a/include/sound/core.h b/include/sound/core.h index 3edc4ab08774..dfef0c9d4b9f 100644 --- a/include/sound/core.h +++ b/include/sound/core.h @@ -96,9 +96,9 @@ struct snd_card { private data */ struct list_head devices; /* devices */ - struct device ctl_dev; /* control device */ + struct device *ctl_dev; /* control device */ unsigned int last_numid; /* last used numeric ID */ - struct rw_semaphore controls_rwsem; /* controls list lock */ + struct rw_semaphore controls_rwsem; /* controls lock (list and values) */ rwlock_t ctl_files_rwlock; /* ctl_files list lock */ int controls_count; /* count of all controls */ size_t user_ctl_alloc_size; // current memory allocation by user controls. @@ -232,14 +232,14 @@ static inline struct device *snd_card_get_device_link(struct snd_card *card) extern int snd_major; extern int snd_ecards_limit; -extern struct class *sound_class; +extern const struct class sound_class; #ifdef CONFIG_SND_DEBUG extern struct dentry *sound_debugfs_root; #endif void snd_request_card(int card); -void snd_device_initialize(struct device *dev, struct snd_card *card); +int snd_device_alloc(struct device **dev_p, struct snd_card *card); int snd_register_device(int type, struct snd_card *card, int dev, const struct file_operations *f_ops, diff --git a/include/sound/cs35l41.h b/include/sound/cs35l41.h index 9ac5918269a5..1bf757901d02 100644 --- a/include/sound/cs35l41.h +++ b/include/sound/cs35l41.h @@ -11,6 +11,7 @@ #define __CS35L41_H #include <linux/regmap.h> +#include <linux/completion.h> #include <linux/firmware/cirrus/cs_dsp.h> #define CS35L41_FIRSTREG 0x00000000 @@ -677,6 +678,7 @@ #define CS35L36_PUP_DONE_IRQ_UNMASK 0x5F #define CS35L36_PUP_DONE_IRQ_MASK 0xBF +#define CS35L41_SYNC_EN_MASK BIT(8) #define CS35L41_AMP_SHORT_ERR 0x80000000 #define CS35L41_BST_SHORT_ERR 0x0100 @@ -686,6 +688,7 @@ #define CS35L41_BST_DCM_UVP_ERR 0x80 #define CS35L41_OTP_BOOT_DONE 0x02 #define CS35L41_PLL_UNLOCK 0x10 +#define CS35L41_PLL_LOCK BIT(1) #define CS35L41_OTP_BOOT_ERR 0x80000000 #define CS35L41_AMP_SHORT_ERR_RLS 0x02 @@ -705,6 +708,8 @@ #define CS35L41_INT1_MASK_DEFAULT 0x7FFCFE3F #define CS35L41_INT1_UNMASK_PUP 0xFEFFFFFF #define CS35L41_INT1_UNMASK_PDN 0xFF7FFFFF +#define CS35L41_INT3_PLL_LOCK_SHIFT 1 +#define CS35L41_INT3_PLL_LOCK_MASK BIT(CS35L41_INT3_PLL_LOCK_SHIFT) #define CS35L41_GPIO_DIR_MASK 0x80000000 #define CS35L41_GPIO_DIR_SHIFT 31 @@ -742,6 +747,11 @@ enum cs35l41_boost_type { CS35L41_INT_BOOST, CS35L41_EXT_BOOST, + CS35L41_SHD_BOOST_ACTV, + CS35L41_SHD_BOOST_PASS, + + // Not present in Binding Documentation, so no system should use this value. + // This value is only used in CLSA0100 Laptop CS35L41_EXT_BOOST_NO_VSPK_SWITCH, }; @@ -819,6 +829,7 @@ enum cs35l41_cspl_mbox_cmd { CSPL_MBOX_CMD_STOP_PRE_REINIT = 4, CSPL_MBOX_CMD_HIBERNATE = 5, CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6, + CSPL_MBOX_CMD_SPK_OUT_ENABLE = 7, CSPL_MBOX_CMD_UNKNOWN_CMD = -1, CSPL_MBOX_CMD_INVALID_SEQUENCE = -2, }; @@ -891,6 +902,7 @@ int cs35l41_exit_hibernate(struct device *dev, struct regmap *regmap); int cs35l41_init_boost(struct device *dev, struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg); bool cs35l41_safe_reset(struct regmap *regmap, enum cs35l41_boost_type b_type); -int cs35l41_global_enable(struct regmap *regmap, enum cs35l41_boost_type b_type, int enable); +int cs35l41_global_enable(struct device *dev, struct regmap *regmap, enum cs35l41_boost_type b_type, + int enable, struct completion *pll_lock, bool firmware_running); #endif /* __CS35L41_H */ diff --git a/include/sound/cs35l56.h b/include/sound/cs35l56.h new file mode 100644 index 000000000000..3950322bf3cb --- /dev/null +++ b/include/sound/cs35l56.h @@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Common definitions for Cirrus Logic CS35L56 smart amp + * + * Copyright (C) 2023 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef __CS35L56_H +#define __CS35L56_H + +#include <linux/firmware/cirrus/cs_dsp.h> +#include <linux/regulator/consumer.h> +#include <linux/regmap.h> + +#define CS35L56_DEVID 0x0000000 +#define CS35L56_REVID 0x0000004 +#define CS35L56_RELID 0x000000C +#define CS35L56_OTPID 0x0000010 +#define CS35L56_SFT_RESET 0x0000020 +#define CS35L56_GLOBAL_ENABLES 0x0002014 +#define CS35L56_BLOCK_ENABLES 0x0002018 +#define CS35L56_BLOCK_ENABLES2 0x000201C +#define CS35L56_REFCLK_INPUT 0x0002C04 +#define CS35L56_GLOBAL_SAMPLE_RATE 0x0002C0C +#define CS35L56_ASP1_ENABLES1 0x0004800 +#define CS35L56_ASP1_CONTROL1 0x0004804 +#define CS35L56_ASP1_CONTROL2 0x0004808 +#define CS35L56_ASP1_CONTROL3 0x000480C +#define CS35L56_ASP1_FRAME_CONTROL1 0x0004810 +#define CS35L56_ASP1_FRAME_CONTROL5 0x0004820 +#define CS35L56_ASP1_DATA_CONTROL1 0x0004830 +#define CS35L56_ASP1_DATA_CONTROL5 0x0004840 +#define CS35L56_DACPCM1_INPUT 0x0004C00 +#define CS35L56_DACPCM2_INPUT 0x0004C08 +#define CS35L56_ASP1TX1_INPUT 0x0004C20 +#define CS35L56_ASP1TX2_INPUT 0x0004C24 +#define CS35L56_ASP1TX3_INPUT 0x0004C28 +#define CS35L56_ASP1TX4_INPUT 0x0004C2C +#define CS35L56_DSP1RX1_INPUT 0x0004C40 +#define CS35L56_DSP1RX2_INPUT 0x0004C44 +#define CS35L56_SWIRE_DP3_CH1_INPUT 0x0004C70 +#define CS35L56_SWIRE_DP3_CH2_INPUT 0x0004C74 +#define CS35L56_SWIRE_DP3_CH3_INPUT 0x0004C78 +#define CS35L56_SWIRE_DP3_CH4_INPUT 0x0004C7C +#define CS35L56_IRQ1_CFG 0x000E000 +#define CS35L56_IRQ1_STATUS 0x000E004 +#define CS35L56_IRQ1_EINT_1 0x000E010 +#define CS35L56_IRQ1_EINT_2 0x000E014 +#define CS35L56_IRQ1_EINT_4 0x000E01C +#define CS35L56_IRQ1_EINT_8 0x000E02C +#define CS35L56_IRQ1_EINT_18 0x000E054 +#define CS35L56_IRQ1_EINT_20 0x000E05C +#define CS35L56_IRQ1_MASK_1 0x000E090 +#define CS35L56_IRQ1_MASK_2 0x000E094 +#define CS35L56_IRQ1_MASK_4 0x000E09C +#define CS35L56_IRQ1_MASK_8 0x000E0AC +#define CS35L56_IRQ1_MASK_18 0x000E0D4 +#define CS35L56_IRQ1_MASK_20 0x000E0DC +#define CS35L56_DSP_VIRTUAL1_MBOX_1 0x0011020 +#define CS35L56_DSP_VIRTUAL1_MBOX_2 0x0011024 +#define CS35L56_DSP_VIRTUAL1_MBOX_3 0x0011028 +#define CS35L56_DSP_VIRTUAL1_MBOX_4 0x001102C +#define CS35L56_DSP_VIRTUAL1_MBOX_5 0x0011030 +#define CS35L56_DSP_VIRTUAL1_MBOX_6 0x0011034 +#define CS35L56_DSP_VIRTUAL1_MBOX_7 0x0011038 +#define CS35L56_DSP_VIRTUAL1_MBOX_8 0x001103C +#define CS35L56_DSP_RESTRICT_STS1 0x00190F0 +#define CS35L56_DSP1_XMEM_PACKED_0 0x2000000 +#define CS35L56_DSP1_XMEM_PACKED_6143 0x2005FFC +#define CS35L56_DSP1_XMEM_UNPACKED32_0 0x2400000 +#define CS35L56_DSP1_XMEM_UNPACKED32_4095 0x2403FFC +#define CS35L56_DSP1_SYS_INFO_ID 0x25E0000 +#define CS35L56_DSP1_SYS_INFO_END 0x25E004C +#define CS35L56_DSP1_AHBM_WINDOW_DEBUG_0 0x25E2040 +#define CS35L56_DSP1_AHBM_WINDOW_DEBUG_1 0x25E2044 +#define CS35L56_DSP1_XMEM_UNPACKED24_0 0x2800000 +#define CS35L56_DSP1_HALO_STATE_A1 0x2801E58 +#define CS35L56_DSP1_HALO_STATE 0x28021E0 +#define CS35L56_DSP1_PM_CUR_STATE_A1 0x2804000 +#define CS35L56_DSP1_PM_CUR_STATE 0x2804308 +#define CS35L56_DSP1_XMEM_UNPACKED24_8191 0x2807FFC +#define CS35L56_DSP1_CORE_BASE 0x2B80000 +#define CS35L56_DSP1_SCRATCH1 0x2B805C0 +#define CS35L56_DSP1_SCRATCH2 0x2B805C8 +#define CS35L56_DSP1_SCRATCH3 0x2B805D0 +#define CS35L56_DSP1_SCRATCH4 0x2B805D8 +#define CS35L56_DSP1_YMEM_PACKED_0 0x2C00000 +#define CS35L56_DSP1_YMEM_PACKED_4604 0x2C047F0 +#define CS35L56_DSP1_YMEM_UNPACKED32_0 0x3000000 +#define CS35L56_DSP1_YMEM_UNPACKED32_3070 0x3002FF8 +#define CS35L56_DSP1_YMEM_UNPACKED24_0 0x3400000 +#define CS35L56_MAIN_RENDER_USER_MUTE 0x3400024 +#define CS35L56_MAIN_RENDER_USER_VOLUME 0x340002C +#define CS35L56_MAIN_POSTURE_NUMBER 0x3400094 +#define CS35L56_PROTECTION_STATUS 0x34000D8 +#define CS35L56_TRANSDUCER_ACTUAL_PS 0x3400150 +#define CS35L56_DSP1_YMEM_UNPACKED24_6141 0x3405FF4 +#define CS35L56_DSP1_PMEM_0 0x3800000 +#define CS35L56_DSP1_PMEM_5114 0x3804FE8 + +/* DEVID */ +#define CS35L56_DEVID_MASK 0x00FFFFFF + +/* REVID */ +#define CS35L56_AREVID_MASK 0x000000F0 +#define CS35L56_MTLREVID_MASK 0x0000000F +#define CS35L56_REVID_B0 0x000000B0 + +/* ASP_ENABLES1 */ +#define CS35L56_ASP_RX2_EN_SHIFT 17 +#define CS35L56_ASP_RX1_EN_SHIFT 16 +#define CS35L56_ASP_TX4_EN_SHIFT 3 +#define CS35L56_ASP_TX3_EN_SHIFT 2 +#define CS35L56_ASP_TX2_EN_SHIFT 1 +#define CS35L56_ASP_TX1_EN_SHIFT 0 + +/* ASP_CONTROL1 */ +#define CS35L56_ASP_BCLK_FREQ_MASK 0x0000003F +#define CS35L56_ASP_BCLK_FREQ_SHIFT 0 + +/* ASP_CONTROL2 */ +#define CS35L56_ASP_RX_WIDTH_MASK 0xFF000000 +#define CS35L56_ASP_RX_WIDTH_SHIFT 24 +#define CS35L56_ASP_TX_WIDTH_MASK 0x00FF0000 +#define CS35L56_ASP_TX_WIDTH_SHIFT 16 +#define CS35L56_ASP_FMT_MASK 0x00000700 +#define CS35L56_ASP_FMT_SHIFT 8 +#define CS35L56_ASP_BCLK_INV_MASK 0x00000040 +#define CS35L56_ASP_FSYNC_INV_MASK 0x00000004 + +/* ASP_CONTROL3 */ +#define CS35L56_ASP1_DOUT_HIZ_CTRL_MASK 0x00000003 + +/* ASP_DATA_CONTROL1 */ +#define CS35L56_ASP_TX_WL_MASK 0x0000003F + +/* ASP_DATA_CONTROL5 */ +#define CS35L56_ASP_RX_WL_MASK 0x0000003F + +/* ASPTXn_INPUT */ +#define CS35L56_ASP_TXn_SRC_MASK 0x0000007F + +/* SWIRETX[1..7]_SRC SDWTXn INPUT */ +#define CS35L56_SWIRETXn_SRC_MASK 0x0000007F + +/* IRQ1_STATUS */ +#define CS35L56_IRQ1_STS_MASK 0x00000001 + +/* IRQ1_EINT_1 */ +#define CS35L56_AMP_SHORT_ERR_EINT1_MASK 0x80000000 + +/* IRQ1_EINT_2 */ +#define CS35L56_DSP_VIRTUAL2_MBOX_WR_EINT1_MASK 0x00200000 + +/* IRQ1_EINT_4 */ +#define CS35L56_OTP_BOOT_DONE_MASK 0x00000002 + +/* IRQ1_EINT_8 */ +#define CS35L56_TEMP_ERR_EINT1_MASK 0x80000000 + +/* Mixer input sources */ +#define CS35L56_INPUT_SRC_NONE 0x00 +#define CS35L56_INPUT_SRC_ASP1RX1 0x08 +#define CS35L56_INPUT_SRC_ASP1RX2 0x09 +#define CS35L56_INPUT_SRC_VMON 0x18 +#define CS35L56_INPUT_SRC_IMON 0x19 +#define CS35L56_INPUT_SRC_ERR_VOL 0x20 +#define CS35L56_INPUT_SRC_CLASSH 0x21 +#define CS35L56_INPUT_SRC_VDDBMON 0x28 +#define CS35L56_INPUT_SRC_VBSTMON 0x29 +#define CS35L56_INPUT_SRC_DSP1TX1 0x32 +#define CS35L56_INPUT_SRC_DSP1TX2 0x33 +#define CS35L56_INPUT_SRC_DSP1TX3 0x34 +#define CS35L56_INPUT_SRC_DSP1TX4 0x35 +#define CS35L56_INPUT_SRC_DSP1TX5 0x36 +#define CS35L56_INPUT_SRC_DSP1TX6 0x37 +#define CS35L56_INPUT_SRC_DSP1TX7 0x38 +#define CS35L56_INPUT_SRC_DSP1TX8 0x39 +#define CS35L56_INPUT_SRC_TEMPMON 0x3A +#define CS35L56_INPUT_SRC_INTERPOLATOR 0x40 +#define CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1 0x44 +#define CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2 0x45 +#define CS35L56_INPUT_MASK 0x7F + +#define CS35L56_NUM_INPUT_SRC 21 + +/* ASP formats */ +#define CS35L56_ASP_FMT_DSP_A 0 +#define CS35L56_ASP_FMT_I2S 2 + +/* ASP HiZ modes */ +#define CS35L56_ASP_UNUSED_HIZ_OFF_HIZ 3 + +/* MAIN_RENDER_ACTUAL_PS */ +#define CS35L56_PS0 0 +#define CS35L56_PS3 3 + +/* CS35L56_DSP_RESTRICT_STS1 */ +#define CS35L56_RESTRICTED_MASK 0x7 + +/* CS35L56_MAIN_RENDER_USER_MUTE */ +#define CS35L56_MAIN_RENDER_USER_MUTE_MASK 1 + +/* CS35L56_MAIN_RENDER_USER_VOLUME */ +#define CS35L56_MAIN_RENDER_USER_VOLUME_MIN -400 +#define CS35L56_MAIN_RENDER_USER_VOLUME_MAX 400 +#define CS35L56_MAIN_RENDER_USER_VOLUME_MASK 0x0000FFC0 +#define CS35L56_MAIN_RENDER_USER_VOLUME_SHIFT 6 +#define CS35L56_MAIN_RENDER_USER_VOLUME_SIGNBIT 9 + +/* CS35L56_MAIN_POSTURE_NUMBER */ +#define CS35L56_MAIN_POSTURE_MIN 0 +#define CS35L56_MAIN_POSTURE_MAX 255 +#define CS35L56_MAIN_POSTURE_MASK CS35L56_MAIN_POSTURE_MAX + +/* CS35L56_PROTECTION_STATUS */ +#define CS35L56_FIRMWARE_MISSING BIT(0) + +/* Software Values */ +#define CS35L56_HALO_STATE_SHUTDOWN 1 +#define CS35L56_HALO_STATE_BOOT_DONE 2 + +#define CS35L56_MBOX_CMD_AUDIO_PLAY 0x0B000001 +#define CS35L56_MBOX_CMD_AUDIO_PAUSE 0x0B000002 +#define CS35L56_MBOX_CMD_AUDIO_REINIT 0x0B000003 +#define CS35L56_MBOX_CMD_HIBERNATE_NOW 0x02000001 +#define CS35L56_MBOX_CMD_WAKEUP 0x02000002 +#define CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE 0x02000003 +#define CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE 0x02000004 +#define CS35L56_MBOX_CMD_SHUTDOWN 0x02000005 +#define CS35L56_MBOX_CMD_SYSTEM_RESET 0x02000007 + +#define CS35L56_MBOX_TIMEOUT_US 5000 +#define CS35L56_MBOX_POLL_US 250 + +#define CS35L56_PS0_POLL_US 500 +#define CS35L56_PS0_TIMEOUT_US 50000 +#define CS35L56_PS3_POLL_US 500 +#define CS35L56_PS3_TIMEOUT_US 300000 + +#define CS35L56_CONTROL_PORT_READY_US 2200 +#define CS35L56_HALO_STATE_POLL_US 1000 +#define CS35L56_HALO_STATE_TIMEOUT_US 50000 +#define CS35L56_HIBERNATE_WAKE_POLL_US 500 +#define CS35L56_HIBERNATE_WAKE_TIMEOUT_US 5000 +#define CS35L56_RESET_PULSE_MIN_US 1100 + +#define CS35L56_SDW1_PLAYBACK_PORT 1 +#define CS35L56_SDW1_CAPTURE_PORT 3 + +#define CS35L56_NUM_BULK_SUPPLIES 3 +#define CS35L56_NUM_DSP_REGIONS 5 + +struct cs35l56_base { + struct device *dev; + struct regmap *regmap; + int irq; + struct mutex irq_lock; + u8 rev; + bool init_done; + bool fw_patched; + bool secured; + bool can_hibernate; + struct gpio_desc *reset_gpio; +}; + +extern struct regmap_config cs35l56_regmap_i2c; +extern struct regmap_config cs35l56_regmap_spi; +extern struct regmap_config cs35l56_regmap_sdw; + +extern const char * const cs35l56_tx_input_texts[CS35L56_NUM_INPUT_SRC]; +extern const unsigned int cs35l56_tx_input_values[CS35L56_NUM_INPUT_SRC]; + +int cs35l56_set_patch(struct cs35l56_base *cs35l56_base); +int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command); +int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base); +int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base); +void cs35l56_wait_control_port_ready(void); +void cs35l56_wait_min_reset_pulse(void); +void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire); +int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq); +irqreturn_t cs35l56_irq(int irq, void *data); +int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base); +int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base); +int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire); +void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp); +int cs35l56_hw_init(struct cs35l56_base *cs35l56_base); +int cs35l56_get_bclk_freq_id(unsigned int freq); +void cs35l56_fill_supply_names(struct regulator_bulk_data *data); + +#endif /* ifndef __CS35L56_H */ diff --git a/include/sound/cs42l43.h b/include/sound/cs42l43.h new file mode 100644 index 000000000000..deb337fc4e8c --- /dev/null +++ b/include/sound/cs42l43.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * CS42L43 CODEC driver external data + * + * Copyright (C) 2022-2023 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef CS42L43_ASOC_EXT_H +#define CS42L43_ASOC_EXT_H + +#define CS42L43_SYSCLK 0 + +#define CS42L43_SYSCLK_MCLK 0 +#define CS42L43_SYSCLK_SDW 1 + +#endif /* CS42L43_ASOC_EXT_H */ diff --git a/include/sound/da7219-aad.h b/include/sound/da7219-aad.h index 24ee7baa2589..41320522daa2 100644 --- a/include/sound/da7219-aad.h +++ b/include/sound/da7219-aad.h @@ -44,6 +44,11 @@ enum da7219_aad_jack_ins_deb { DA7219_AAD_JACK_INS_DEB_1S, }; +enum da7219_aad_jack_ins_det_pty { + DA7219_AAD_JACK_INS_DET_PTY_LOW = 0, + DA7219_AAD_JACK_INS_DET_PTY_HIGH, +}; + enum da7219_aad_jack_det_rate { DA7219_AAD_JACK_DET_RATE_32_64MS = 0, DA7219_AAD_JACK_DET_RATE_64_128MS, @@ -80,6 +85,7 @@ struct da7219_aad_pdata { enum da7219_aad_btn_cfg btn_cfg; enum da7219_aad_mic_det_thr mic_det_thr; enum da7219_aad_jack_ins_deb jack_ins_deb; + enum da7219_aad_jack_ins_det_pty jack_ins_det_pty; enum da7219_aad_jack_det_rate jack_det_rate; enum da7219_aad_jack_rem_deb jack_rem_deb; diff --git a/include/sound/designware_i2s.h b/include/sound/designware_i2s.h index 80d275b9ae0d..f6803205a9fb 100644 --- a/include/sound/designware_i2s.h +++ b/include/sound/designware_i2s.h @@ -21,6 +21,8 @@ struct i2s_clk_config_data { u32 sample_rate; }; +struct dw_i2s_dev; + struct i2s_platform_data { #define DWC_I2S_PLAY (1 << 0) #define DWC_I2S_RECORD (1 << 1) @@ -42,6 +44,7 @@ struct i2s_platform_data { void *capture_dma_data; bool (*filter)(struct dma_chan *chan, void *slave); int (*i2s_clk_cfg)(struct i2s_clk_config_data *config); + int (*i2s_pd_init)(struct dw_i2s_dev *dev); }; struct i2s_dma_data { diff --git a/include/sound/dmaengine_pcm.h b/include/sound/dmaengine_pcm.h index 2df54cf02cb3..c9a8bce9a785 100644 --- a/include/sound/dmaengine_pcm.h +++ b/include/sound/dmaengine_pcm.h @@ -142,7 +142,7 @@ struct snd_dmaengine_pcm_config { struct snd_pcm_substream *substream); int (*process)(struct snd_pcm_substream *substream, int channel, unsigned long hwoff, - void *buf, unsigned long bytes); + struct iov_iter *buf, unsigned long bytes); dma_filter_fn compat_filter_fn; struct device *dma_dev; const char *chan_names[SNDRV_PCM_STREAM_LAST + 1]; diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h index 39787fecc8d9..1af9e6819392 100644 --- a/include/sound/emu10k1.h +++ b/include/sound/emu10k1.h @@ -25,13 +25,9 @@ /* ------------------- DEFINES -------------------- */ #define EMUPAGESIZE 4096 -#define MAXREQVOICES 8 #define MAXPAGES0 4096 /* 32 bit mode */ #define MAXPAGES1 8192 /* 31 bit mode */ -#define RESERVED 0 -#define NUM_MIDI 16 #define NUM_G 64 /* use all channels */ -#define NUM_FXSENDS 4 #define NUM_EFX_PLAYBACK 16 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */ @@ -39,10 +35,38 @@ #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */ #define TMEMSIZE 256*1024 -#define TMEMSIZEREG 4 #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL)) +// This is used to define hardware bit-fields (sub-registers) by combining +// the bit shift and count with the actual register address. The passed +// mask must represent a single run of adjacent bits. +// The non-concatenating (_NC) variant should be used directly only for +// sub-registers that do not follow the <register>_<field> naming pattern. +#define SUB_REG_NC(reg, field, mask) \ + enum { \ + field ## _MASK = mask, \ + field = reg | \ + (__builtin_ctz(mask) << 16) | \ + (__builtin_popcount(mask) << 24), \ + }; +#define SUB_REG(reg, field, mask) SUB_REG_NC(reg, reg ## _ ## field, mask) + +// Macros for manipulating values of bit-fields declared using the above macros. +// Best used with constant register addresses, as otherwise quite some code is +// generated. The actual register read/write functions handle combined addresses +// automatically, so use of these macros conveys no advantage when accessing a +// single sub-register at a time. +#define REG_SHIFT(r) (((r) >> 16) & 0x1f) +#define REG_SIZE(r) (((r) >> 24) & 0x1f) +#define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U) +#define REG_MASK(r) (REG_MASK0(r) << REG_SHIFT(r)) +#define REG_VAL_GET(r, v) ((v & REG_MASK(r)) >> REG_SHIFT(r)) +#define REG_VAL_PUT(r, v) ((v) << REG_SHIFT(r)) + +// List terminator for snd_emu10k1_ptr_write_multiple() +#define REGLIST_END ~0 + // Audigy specify registers are prefixed with 'A_' /************************************************************************************************/ @@ -66,8 +90,8 @@ /* the relevant bits and zero to the other bits */ #define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes to interrupt */ -#define IPR_GPIOMSG 0x20000000 /* GPIO message interrupt (RE'd, still not sure - which INTE bits enable it) */ +#define IPR_WATERMARK_REACHED 0x40000000 +#define IPR_A_GPIO 0x20000000 /* GPIO input pin change */ /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */ #define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */ @@ -95,11 +119,15 @@ #define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */ #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */ #define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */ + /* The interrupt is triggered shortly after */ + /* CCR_READADDRESS has crossed the boundary; */ + /* due to the cache, this runs ahead of the */ + /* actual playback position. */ #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */ /* highest set channel in CLIPL, CLIPH, HLIPL, */ - /* or HLIPH. When IP is written with CL set, */ + /* or HLIPH. When IPR is written with CL set, */ /* the bit in H/CLIPL or H/CLIPH corresponding */ - /* to the CIN value written will be cleared. */ + /* to the CN value written will be cleared. */ #define INTE 0x0c /* Interrupt enable register */ #define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */ @@ -127,10 +155,14 @@ /* behavior and possibly random segfaults and */ /* lockups if enabled. */ +#define INTE_A_GPIOENABLE 0x00040000 /* Enable GPIO input change interrupts */ + /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */ #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */ #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */ +#define INTE_A_SPDIF_BUFFULL_ENABLE 0x00008000 +#define INTE_A_SPDIF_HALFBUFFULL_ENABLE 0x00004000 #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */ /* NOTE: This bit must always be enabled */ @@ -149,9 +181,8 @@ #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */ #define WC 0x10 /* Wall Clock register */ -#define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */ -#define WC_SAMPLECOUNTER 0x14060010 -#define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */ +SUB_REG(WC, SAMPLECOUNTER, 0x03FFFFC0) /* Sample periods elapsed since reset */ +SUB_REG(WC, CURRENTCHANNEL, 0x0000003F) /* Channel [0..63] currently being serviced */ /* NOTE: Each channel takes 1/64th of a sample */ /* period to be serviced. */ @@ -180,6 +211,7 @@ #define HCFG_CODECFORMAT_MASK 0x00030000 /* CODEC format */ /* Specific to Alice2, CA0102 */ + #define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */ #define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */ #define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */ @@ -200,9 +232,8 @@ /* I2S format input */ /* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */ - - /* Older chips */ + #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */ #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */ #define HCFG_GPINPUT0 0x00004000 /* External pin112 */ @@ -225,9 +256,8 @@ /* async audio source */ #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */ /* NOTE: This should generally never be used. */ -#define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */ +SUB_REG(HCFG, LOCKTANKCACHE, 0x00000004) /* 1 = Cancel bustmaster accesses to tankcache */ /* NOTE: This should generally never be used. */ -#define HCFG_LOCKTANKCACHE 0x01020014 #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */ /* NOTE: This is a 'cheap' way to implement a */ /* master mute function on the mute button, and */ @@ -238,7 +268,7 @@ /* Should be set to 1 when the EMU10K1 is */ /* completely initialized. */ -//For Audigy, MPU port move to 0x70-0x74 ptr register +// On Audigy, the MPU port moved to the 0x70-0x74 ptr registers #define MUDATA 0x18 /* MPU401 data register (8 bits) */ @@ -251,11 +281,17 @@ #define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */ #define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */ -#define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */ -#define A_GPINPUT_MASK 0xff00 +#define A_GPIO 0x18 /* GPIO on Audigy card (16bits) */ +#define A_GPINPUT_MASK 0xff00 /* Alice/2 has 8 input pins */ +#define A3_GPINPUT_MASK 0x3f00 /* ... while Tina/2 has only 6 */ #define A_GPOUTPUT_MASK 0x00ff +// The GPIO port is used for I/O config on Sound Blasters; +// card-specific info can be found in the emu_chip_details table. +// On E-MU cards the port is used as the interface to the FPGA. + // Audigy output/GPIO stuff taken from the kX drivers +#define A_IOCFG A_GPIO #define A_IOCFG_GPOUT0 0x0044 /* analog/digital */ #define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */ #define A_IOCFG_ENABLE_DIGITAL 0x0004 @@ -271,19 +307,12 @@ #define A_IOCFG_REAR_JACK 0x8000 #define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */ -/* outputs: - * for audigy2 platinum: 0xa00 - * for a2 platinum ex: 0x1c00 - * for a1 platinum: 0x0 - */ - #define TIMER 0x1a /* Timer terminal count register */ /* NOTE: After the rate is changed, a maximum */ /* of 1024 sample periods should be allowed */ /* before the new rate is guaranteed accurate. */ -#define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */ +#define TIMER_RATE_MASK 0x03ff /* Timer interrupt rate in sample periods */ /* 0 == 1024 periods, [1..4] are not useful */ -#define TIMER_RATE 0x0a00001a #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */ @@ -317,7 +346,7 @@ /* 0x00000000 2-channel output. */ /* 0x00000200 8-channel output. */ /* 0x00000004 pauses stream/irq fail. */ - /* Rest of bits no nothing to sound output */ + /* Rest of bits do nothing to sound output */ /* bit 0: Enable P16V audio. * bit 1: Lock P16V record memory cache. * bit 2: Lock P16V playback memory cache. @@ -331,6 +360,7 @@ */ #define IPR3 0x38 /* Cdif interrupt pending register */ #define INTE3 0x3c /* Cdif interrupt enable register. */ + /************************************************************************************************/ /* PCI function 1 registers, address = <val> + PCIBASE1 */ /************************************************************************************************/ @@ -349,61 +379,82 @@ #define JOYSTICK_BUTTONS 0x0f /* Joystick button data */ #define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */ - /********************************************************************************************************/ /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */ /********************************************************************************************************/ +// No official documentation was released for EMU10K1, but some info +// about playback can be extrapolated from the EMU8K documents: +// "AWE32/EMU8000 Programmer’s Guide" (emu8kpgm.pdf) - registers +// "AWE32 Developer's Information Pack" (adip301.pdf) - high-level view + +// The short version: +// - The engine has 64 playback channels, also called voices. The channels +// operate independently, except when paired for stereo (see below). +// - PCM samples are fetched into the cache; see description of CD0 below. +// - Samples are consumed at the rate CPF_CURRENTPITCH. +// - 8-bit samples are transformed upon use: cooked = (raw ^ 0x80) << 8 +// - 8 samples are read at CCR_READADDRESS:CPF_FRACADDRESS and interpolated +// according to CCCA_INTERPROM_*. With CCCA_INTERPROM_0 selected and a zero +// CPF_FRACADDRESS, this results in CCR_READADDRESS[3] being used verbatim. +// - The value is multiplied by CVCF_CURRENTVOL. +// - The value goes through a filter with cutoff CVCF_CURRENTFILTER; +// delay stages Z1 and Z2. +// - The value is added by so-called `sends` to 4 (EMU10K1) / 8 (EMU10K2) +// of the 16 (EMU10K1) / 64 (EMU10K2) FX bus accumulators via FXRT*, +// multiplied by a per-send amount (*_FXSENDAMOUNT_*). +// The scaling of the send amounts is exponential-ish. +// - The DSP has a go at FXBUS* and outputs the values to EXTOUT* or EMU32OUT*. +// - The pitch, volume, and filter cutoff can be modulated by two envelope +// engines and two low frequency oscillators. +// - To avoid abrupt changes to the parameters (which may cause audible +// distortion), the modulation engine sets the target registers, towards +// which the current registers "swerve" gradually. + +// For the odd channel in a stereo pair, these registers are meaningless: +// CPF_STEREO, CPF_CURRENTPITCH, PTRX_PITCHTARGET, CCR_CACHEINVALIDSIZE, +// PSST_LOOPSTARTADDR, DSL_LOOPENDADDR, CCCA_CURRADDR +// The somewhat non-obviously still meaningful ones are: +// CPF_STOP, CPF_FRACADDRESS, CCR_READADDRESS (!), +// CCCA_INTERPROM, CCCA_8BITSELECT (!) +// (The envelope engine is ignored here, as stereo matters only for verbatim playback.) + #define CPF 0x00 /* Current pitch and fraction register */ -#define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */ -#define CPF_CURRENTPITCH 0x10100000 +SUB_REG(CPF, CURRENTPITCH, 0xffff0000) /* Current pitch (linear, 0x4000 == unity pitch shift) */ #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */ -#define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */ +SUB_REG(CPF, STOP, 0x00004000) /* 1 = Current pitch forced to 0 */ + /* Can be set only while matching bit in SOLEx is 1 */ #define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */ #define PTRX 0x01 /* Pitch target and send A/B amounts register */ -#define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */ -#define PTRX_PITCHTARGET 0x10100001 -#define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */ -#define PTRX_FXSENDAMOUNT_A 0x08080001 -#define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */ -#define PTRX_FXSENDAMOUNT_B 0x08000001 +SUB_REG(PTRX, PITCHTARGET, 0xffff0000) /* Pitch target of specified channel */ +SUB_REG(PTRX, FXSENDAMOUNT_A, 0x0000ff00) /* Linear level of channel output sent to FX send bus A */ +SUB_REG(PTRX, FXSENDAMOUNT_B, 0x000000ff) /* Linear level of channel output sent to FX send bus B */ +// Note: the volumes are raw multpliers, so real 100% is impossible. #define CVCF 0x02 /* Current volume and filter cutoff register */ -#define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */ -#define CVCF_CURRENTVOL 0x10100002 -#define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */ -#define CVCF_CURRENTFILTER 0x10000002 +SUB_REG(CVCF, CURRENTVOL, 0xffff0000) /* Current linear volume of specified channel */ +SUB_REG(CVCF, CURRENTFILTER, 0x0000ffff) /* Current filter cutoff frequency of specified channel */ #define VTFT 0x03 /* Volume target and filter cutoff target register */ -#define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */ -#define VTFT_VOLUMETARGET 0x10100003 -#define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */ -#define VTFT_FILTERTARGET 0x10000003 +SUB_REG(VTFT, VOLUMETARGET, 0xffff0000) /* Volume target of specified channel */ +SUB_REG(VTFT, FILTERTARGET, 0x0000ffff) /* Filter cutoff target of specified channel */ #define Z1 0x05 /* Filter delay memory 1 register */ #define Z2 0x04 /* Filter delay memory 2 register */ #define PSST 0x06 /* Send C amount and loop start address register */ -#define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */ - -#define PSST_FXSENDAMOUNT_C 0x08180006 +SUB_REG(PSST, FXSENDAMOUNT_C, 0xff000000) /* Linear level of channel output sent to FX send bus C */ +SUB_REG(PSST, LOOPSTARTADDR, 0x00ffffff) /* Loop start address of the specified channel */ -#define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */ -#define PSST_LOOPSTARTADDR 0x18000006 - -#define DSL 0x07 /* Send D amount and loop start address register */ -#define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */ - -#define DSL_FXSENDAMOUNT_D 0x08180007 - -#define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */ -#define DSL_LOOPENDADDR 0x18000007 +#define DSL 0x07 /* Send D amount and loop end address register */ +SUB_REG(DSL, FXSENDAMOUNT_D, 0xff000000) /* Linear level of channel output sent to FX send bus D */ +SUB_REG(DSL, LOOPENDADDR, 0x00ffffff) /* Loop end address of the specified channel */ #define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */ -#define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */ -#define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */ +SUB_REG(CCCA, RESONANCE, 0xf0000000) /* Lowpass filter resonance (Q) height */ +#define CCCA_INTERPROM_MASK 0x0e000000 /* Selects passband of interpolation ROM */ /* 1 == full band, 7 == lowpass */ /* ROM 0 is used when pitch shifting downward or less */ /* then 3 semitones upward. Increasingly higher ROM */ @@ -418,25 +469,25 @@ #define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */ #define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */ #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */ -#define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */ -#define CCCA_CURRADDR 0x18000008 + /* 8-bit samples are unsigned, 16-bit ones signed */ +SUB_REG(CCCA, CURRADDR, 0x00ffffff) /* Current address of the selected channel */ #define CCR 0x09 /* Cache control register */ -#define CCR_CACHEINVALIDSIZE 0x07190009 -#define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */ +SUB_REG(CCR, CACHEINVALIDSIZE, 0xfe000000) /* Number of invalid samples before the read address */ #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */ #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */ + /* Auto-set from CPF_STEREO_MASK */ #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */ -#define CCR_READADDRESS 0x06100009 -#define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */ -#define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */ + /* Auto-set from CCCA_8BITSELECT */ +SUB_REG(CCR, READADDRESS, 0x003f0000) /* Next cached sample to play */ +SUB_REG(CCR, LOOPINVALSIZE, 0x0000fe00) /* Number of invalid samples in cache prior to loop */ /* NOTE: This is valid only if CACHELOOPFLAG is set */ #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */ -#define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */ +SUB_REG(CCR, CACHELOOPADDRHI, 0x000000ff) /* CLP_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */ #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */ /* NOTE: This register is normally not used */ -#define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */ +SUB_REG(CLP, CACHELOOPADDR, 0x0000ffff) /* Cache loop address low word */ #define FXRT 0x0b /* Effects send routing register */ /* NOTE: It is illegal to assign the same routing to */ @@ -446,9 +497,7 @@ #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */ #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */ -#define A_HR 0x0b /* High Resolution. 24bit playback from host to DSP. */ #define MAPA 0x0c /* Cache map A */ - #define MAPB 0x0d /* Cache map B */ #define MAP_PTE_MASK0 0xfffff000 /* The 20 MSBs of the PTE indexed by the PTI */ @@ -457,22 +506,22 @@ #define MAP_PTE_MASK1 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */ #define MAP_PTI_MASK1 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */ -/* 0x0e, 0x0f: Not used */ +/* 0x0e, 0x0f: Internal state, at least on Audigy */ #define ENVVOL 0x10 /* Volume envelope register */ #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */ /* 0x8000-n == 666*n usec delay */ #define ATKHLDV 0x11 /* Volume envelope hold and attack register */ -#define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */ +#define ATKHLDV_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */ #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */ #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */ /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */ #define DCYSUSV 0x12 /* Volume envelope sustain and decay register */ -#define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */ +#define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */ #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */ -#define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */ +#define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 0 = Inhibit envelope engine from writing values in */ /* this channel and from writing to pitch, filter and */ /* volume targets. */ #define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */ @@ -487,13 +536,13 @@ /* 0x8000-n == 666*n usec delay */ #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */ -#define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */ +#define ATKHLDM_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */ #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */ #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */ /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */ #define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */ -#define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */ +#define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */ #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */ #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */ /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */ @@ -508,34 +557,30 @@ #define IP_UNITY 0x0000e000 /* Unity pitch shift */ #define IFATN 0x19 /* Initial filter cutoff and attenuation register */ -#define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */ +SUB_REG(IFATN, FILTERCUTOFF, 0x0000ff00) /* Initial filter cutoff frequency in exponential units */ /* 6 most significant bits are semitones */ /* 2 least significant bits are fractions */ -#define IFATN_FILTERCUTOFF 0x08080019 -#define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */ -#define IFATN_ATTENUATION 0x08000019 - +SUB_REG(IFATN, ATTENUATION, 0x000000ff) /* Initial attenuation in 0.375dB steps */ #define PEFE 0x1a /* Pitch envelope and filter envelope amount register */ -#define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */ +SUB_REG(PEFE, PITCHAMOUNT, 0x0000ff00) /* Pitch envlope amount */ /* Signed 2's complement, +/- one octave peak extremes */ -#define PEFE_PITCHAMOUNT 0x0808001a -#define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */ +SUB_REG(PEFE, FILTERAMOUNT, 0x000000ff) /* Filter envlope amount */ /* Signed 2's complement, +/- six octaves peak extremes */ -#define PEFE_FILTERAMOUNT 0x0800001a + + #define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */ #define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */ /* Signed 2's complement, +/- one octave extremes */ #define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */ /* Signed 2's complement, +/- three octave extremes */ - #define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */ #define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */ /* Signed 2's complement, with +/- 12dB extremes */ - #define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */ /* ??Hz steps, maximum of ?? Hz. */ + #define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */ #define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */ /* Signed 2's complement, +/- one octave extremes */ @@ -549,24 +594,22 @@ /* 0x1f: not used */ -#define CD0 0x20 /* Cache data 0 register */ -#define CD1 0x21 /* Cache data 1 register */ -#define CD2 0x22 /* Cache data 2 register */ -#define CD3 0x23 /* Cache data 3 register */ -#define CD4 0x24 /* Cache data 4 register */ -#define CD5 0x25 /* Cache data 5 register */ -#define CD6 0x26 /* Cache data 6 register */ -#define CD7 0x27 /* Cache data 7 register */ -#define CD8 0x28 /* Cache data 8 register */ -#define CD9 0x29 /* Cache data 9 register */ -#define CDA 0x2a /* Cache data A register */ -#define CDB 0x2b /* Cache data B register */ -#define CDC 0x2c /* Cache data C register */ -#define CDD 0x2d /* Cache data D register */ -#define CDE 0x2e /* Cache data E register */ -#define CDF 0x2f /* Cache data F register */ - -/* 0x30-3f seem to be the same as 0x20-2f */ +// 32 cache registers (== 128 bytes) per channel follow. +// In stereo mode, the two channels' caches are concatenated into one, +// and hold the interleaved frames. +// The cache holds 64 frames, so the upper half is not used in 8-bit mode. +// All registers mentioned below count in frames. +// The cache is a ring buffer; CCR_READADDRESS operates modulo 64. +// The cache is filled from (CCCA_CURRADDR - CCR_CACHEINVALIDSIZE) +// into (CCR_READADDRESS - CCR_CACHEINVALIDSIZE). +// The engine has a fetch threshold of 32 bytes, so it tries to keep +// CCR_CACHEINVALIDSIZE below 8 (16-bit stereo), 16 (16-bit mono, +// 8-bit stereo), or 32 (8-bit mono). The actual transfers are pretty +// unpredictable, especially if several voices are running. +// Frames are consumed at CCR_READADDRESS, which is incremented afterwards, +// along with CCCA_CURRADDR and CCR_CACHEINVALIDSIZE. This implies that the +// actual playback position always lags CCCA_CURRADDR by exactly 64 frames. +#define CD0 0x20 /* Cache data registers 0 .. 0x1f */ #define PTB 0x40 /* Page table base register */ #define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */ @@ -603,20 +646,6 @@ /* is 16bit, 48KHz only. All 32 channels can be enabled */ /* simultaneously. */ -#define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */ -#define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */ -#define FXWC_DEFAULTROUTE_A (1<<12) -#define FXWC_DEFAULTROUTE_D (1<<13) -#define FXWC_ADCLEFT (1<<18) -#define FXWC_CDROMSPDIFLEFT (1<<18) -#define FXWC_ADCRIGHT (1<<19) -#define FXWC_CDROMSPDIFRIGHT (1<<19) -#define FXWC_MIC (1<<20) -#define FXWC_ZOOMLEFT (1<<20) -#define FXWC_ZOOMRIGHT (1<<21) -#define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */ -#define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */ - #define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */ #define TCBS 0x44 /* Tank cache buffer size register */ @@ -639,7 +668,7 @@ #define FXBA 0x47 /* FX Buffer Address */ #define FXBA_MASK 0xfffff000 /* 20 bit base address */ -#define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */ +#define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */ #define MICBS 0x49 /* Microphone buffer size register */ @@ -647,9 +676,7 @@ #define FXBS 0x4b /* FX buffer size register */ -/* register: 0x4c..4f: ffff-ffff current amounts, per-channel */ - -/* The following mask values define the size of the ADC, MIX and FX buffers in bytes */ +/* The following mask values define the size of the ADC, MIC and FX buffers in bytes */ #define ADCBS_BUFSIZE_NONE 0x00000000 #define ADCBS_BUFSIZE_384 0x00000001 #define ADCBS_BUFSIZE_448 0x00000002 @@ -683,38 +710,29 @@ #define ADCBS_BUFSIZE_57344 0x0000001e #define ADCBS_BUFSIZE_65536 0x0000001f -/* Current Send B, A Amounts */ -#define A_CSBA 0x4c - -/* Current Send D, C Amounts */ -#define A_CSDC 0x4d +// On Audigy, the FX send amounts are not applied instantly, but determine +// targets towards which the following registers swerve gradually. +#define A_CSBA 0x4c /* FX send B & A current amounts */ +#define A_CSDC 0x4d /* FX send D & C current amounts */ +#define A_CSFE 0x4e /* FX send F & E current amounts */ +#define A_CSHG 0x4f /* FX send H & G current amounts */ -/* Current Send F, E Amounts */ -#define A_CSFE 0x4e +// NOTE: 0x50,51,52: 64-bit (split over voices 0 & 1) +#define CDCS 0x50 /* CD-ROM digital channel status register */ -/* Current Send H, G Amounts */ -#define A_CSHG 0x4f +#define GPSCS 0x51 /* General Purpose SPDIF channel status register */ +// Corresponding EMU10K1_DBG_* constants are in the public header +#define DBG 0x52 -#define CDCS 0x50 /* CD-ROM digital channel status register */ +#define A_SPSC 0x52 /* S/PDIF Input C Channel Status */ -#define GPSCS 0x51 /* General Purpose SPDIF channel status register*/ +#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ -#define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ +// Corresponding A_DBG_* constants are in the public header +#define A_DBG 0x53 -/* S/PDIF Input C Channel Status */ -#define A_SPSC 0x52 - -#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ - -#define A_DBG 0x53 -#define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */ -#define A_DBG_ZC 0x40000000 /* zero tram counter */ -#define A_DBG_STEP_ADDR 0x000003ff -#define A_DBG_SATURATION_OCCURED 0x20000000 -#define A_DBG_SATURATION_ADDR 0x0ffc0000 - -// NOTE: 0x54,55,56: 64-bit +// NOTE: 0x54,55,56: 64-bit (split over voices 0 & 1) #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */ #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */ @@ -747,17 +765,17 @@ /* 0x57: Not used */ -/* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */ +/* The 32-bit CLIx and SOLEx registers all have one bit per channel control/status */ #define CLIEL 0x58 /* Channel loop interrupt enable low register */ - #define CLIEH 0x59 /* Channel loop interrupt enable high register */ #define CLIPL 0x5a /* Channel loop interrupt pending low register */ - #define CLIPH 0x5b /* Channel loop interrupt pending high register */ +// These cause CPF_STOP_MASK to be set shortly after CCCA_CURRADDR passes DSL_LOOPENDADDR. +// Subsequent changes to the address registers don't resume; clearing the bit here or in CPF does. +// The registers are NOT synchronized; the next serviced channel picks up immediately. #define SOLEL 0x5c /* Stop on loop enable low register */ - #define SOLEH 0x5d /* Stop on loop enable high register */ #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */ @@ -767,13 +785,12 @@ #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */ #define AC97SLOT 0x5f /* additional AC97 slots enable bits */ -#define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */ -#define AC97SLOT_REAR_LEFT 0x02 /* Rear right */ -#define AC97SLOT_CNTR 0x10 /* Center enable */ -#define AC97SLOT_LFE 0x20 /* LFE enable */ +#define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */ +#define AC97SLOT_REAR_LEFT 0x02 /* Rear right */ +#define AC97SLOT_CNTR 0x10 /* Center enable */ +#define AC97SLOT_LFE 0x20 /* LFE enable */ -/* PCB Revision */ -#define A_PCB 0x5f +#define A_PCB 0x5f /* PCB Revision */ // NOTE: 0x60,61,62: 64-bit #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */ @@ -796,44 +813,35 @@ #define SRCS_SPDIFRATE_96 0x00080000 #define MICIDX 0x63 /* Microphone recording buffer index register */ -#define MICIDX_MASK 0x0000ffff /* 16-bit value */ -#define MICIDX_IDX 0x10000063 +SUB_REG(MICIDX, IDX, 0x0000ffff) #define ADCIDX 0x64 /* ADC recording buffer index register */ -#define ADCIDX_MASK 0x0000ffff /* 16 bit index field */ -#define ADCIDX_IDX 0x10000064 +SUB_REG(ADCIDX, IDX, 0x0000ffff) #define A_ADCIDX 0x63 -#define A_ADCIDX_IDX 0x10000063 +SUB_REG(A_ADCIDX, IDX, 0x0000ffff) #define A_MICIDX 0x64 -#define A_MICIDX_IDX 0x10000064 +SUB_REG(A_MICIDX, IDX, 0x0000ffff) #define FXIDX 0x65 /* FX recording buffer index register */ -#define FXIDX_MASK 0x0000ffff /* 16-bit value */ -#define FXIDX_IDX 0x10000065 +SUB_REG(FXIDX, IDX, 0x0000ffff) -/* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */ +/* The 32-bit HLIEx and HLIPx registers all have one bit per channel control/status */ #define HLIEL 0x66 /* Channel half loop interrupt enable low register */ - #define HLIEH 0x67 /* Channel half loop interrupt enable high register */ #define HLIPL 0x68 /* Channel half loop interrupt pending low register */ - #define HLIPH 0x69 /* Channel half loop interrupt pending high register */ -/* S/PDIF Host Record Index (bypasses SRC) */ -#define A_SPRI 0x6a -/* S/PDIF Host Record Address */ -#define A_SPRA 0x6b -/* S/PDIF Host Record Control */ -#define A_SPRC 0x6c -/* Delayed Interrupt Counter & Enable */ -#define A_DICE 0x6d -/* Tank Table Base */ -#define A_TTB 0x6e -/* Tank Delay Offset */ -#define A_TDOF 0x6f +#define A_SPRI 0x6a /* S/PDIF Host Record Index (bypasses SRC) */ +#define A_SPRA 0x6b /* S/PDIF Host Record Address */ +#define A_SPRC 0x6c /* S/PDIF Host Record Control */ + +#define A_DICE 0x6d /* Delayed Interrupt Counter & Enable */ + +#define A_TTB 0x6e /* Tank Table Base */ +#define A_TDOF 0x6f /* Tank Delay Offset */ /* This is the MPU port on the card (via the game port) */ #define A_MUDATA1 0x70 @@ -846,48 +854,58 @@ #define A_MUSTAT2 A_MUCMD2 /* The next two are the Audigy equivalent of FXWC */ -/* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */ +/* the Audigy can record any output (16bit, 48kHz, up to 64 channels simultaneously) */ /* Each bit selects a channel for recording */ #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */ #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */ -/* Extended Hardware Control */ -#define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */ -#define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */ -#define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */ -#define A_SAMPLE_RATE_UNKNOWN 0xf0030001 /* Bits that can be set, but have unknown use. */ +#define A_EHC 0x76 /* Extended Hardware Control */ + +#define A_SPDIF_SAMPLERATE A_EHC /* Set the sample rate of SPDIF output */ #define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */ -#define A_SPDIF_48000 0x00000000 +#define A_SPDIF_48000 0x00000000 /* kX calls this BYPASS */ #define A_SPDIF_192000 0x00000020 #define A_SPDIF_96000 0x00000040 #define A_SPDIF_44100 0x00000080 +#define A_SPDIF_MUTED 0x000000c0 + +SUB_REG_NC(A_EHC, A_I2S_CAPTURE_RATE, 0x00000e00) /* This sets the capture PCM rate, but it is */ + /* unclear if this sets the ADC rate as well. */ +#define A_I2S_CAPTURE_48000 0x0 +#define A_I2S_CAPTURE_192000 0x1 +#define A_I2S_CAPTURE_96000 0x2 +#define A_I2S_CAPTURE_44100 0x4 + +#define A_EHC_SRC48_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */ +#define A_EHC_SRC48_BYPASS 0x00000000 +#define A_EHC_SRC48_192 0x00002000 +#define A_EHC_SRC48_96 0x00004000 +#define A_EHC_SRC48_44 0x00008000 +#define A_EHC_SRC48_MUTED 0x0000c000 + +#define A_EHC_P17V_TVM 0x00000001 /* Tank virtual memory mode */ +#define A_EHC_P17V_SEL0_MASK 0x00030000 /* Aka A_EHC_P16V_PB_RATE; 00: 48, 01: 44.1, 10: 96, 11: 192 */ +#define A_EHC_P17V_SEL1_MASK 0x000c0000 +#define A_EHC_P17V_SEL2_MASK 0x00300000 +#define A_EHC_P17V_SEL3_MASK 0x00c00000 + +#define A_EHC_ASYNC_BYPASS 0x80000000 + +#define A_SRT3 0x77 /* I2S0 Sample Rate Tracker Status */ +#define A_SRT4 0x78 /* I2S1 Sample Rate Tracker Status */ +#define A_SRT5 0x79 /* I2S2 Sample Rate Tracker Status */ +/* - default to 0x01080000 on my audigy 2 ZS --rlrevell */ -#define A_I2S_CAPTURE_RATE_MASK 0x00000e00 /* This sets the capture PCM rate, but it is */ -#define A_I2S_CAPTURE_48000 0x00000000 /* unclear if this sets the ADC rate as well. */ -#define A_I2S_CAPTURE_192000 0x00000200 -#define A_I2S_CAPTURE_96000 0x00000400 -#define A_I2S_CAPTURE_44100 0x00000800 - -#define A_PCM_RATE_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */ -#define A_PCM_48000 0x00000000 -#define A_PCM_192000 0x00002000 -#define A_PCM_96000 0x00004000 -#define A_PCM_44100 0x00008000 - -/* I2S0 Sample Rate Tracker Status */ -#define A_SRT3 0x77 - -/* I2S1 Sample Rate Tracker Status */ -#define A_SRT4 0x78 +#define A_SRT_ESTSAMPLERATE 0x001fffff +#define A_SRT_RATELOCKED 0x01000000 -/* I2S2 Sample Rate Tracker Status */ -#define A_SRT5 0x79 -/* - default to 0x01080000 on my audigy 2 ZS --rlrevell */ +#define A_TTDA 0x7a /* Tank Table DMA Address */ +#define A_TTDD 0x7b /* Tank Table DMA Data */ -/* Tank Table DMA Address */ -#define A_TTDA 0x7a -/* Tank Table DMA Data */ -#define A_TTDD 0x7b +// In A_FXRT1 & A_FXRT2, the 0x80 bit of each byte completely disables the +// filter (CVCF_CURRENTFILTER) for the corresponding channel. There is no +// effect on the volume (CVCF_CURRENTVOLUME) or the interpolator's filter +// (CCCA_INTERPROM_MASK). #define A_FXRT2 0x7c #define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */ @@ -900,8 +918,7 @@ #define A_FXSENDAMOUNT_F_MASK 0x00FF0000 #define A_FXSENDAMOUNT_G_MASK 0x0000FF00 #define A_FXSENDAMOUNT_H_MASK 0x000000FF -/* 0x7c, 0x7e "high bit is used for filtering" */ - + /* The send amounts for this one are the same as used with the emu10k1 */ #define A_FXRT1 0x7e #define A_FXRT_CHANNELA 0x0000003f @@ -910,55 +927,56 @@ #define A_FXRT_CHANNELD 0x3f000000 /* 0x7f: Not used */ -/* Each FX general purpose register is 32 bits in length, all bits are used */ -#define FXGPREGBASE 0x100 /* FX general purpose registers base */ -#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */ - -#define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */ -#define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */ - -/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */ -/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */ -/* locations are for external TRAM. */ -#define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */ -#define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */ - -/* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */ -#define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */ -#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */ -#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */ -#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */ -#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */ -#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */ -#define MICROCODEBASE 0x400 /* Microcode data base address */ +/* The public header defines the GPR and TRAM base addresses that + * are valid for _both_ CPU and DSP addressing. */ /* Each DSP microcode instruction is mapped into 2 doublewords */ /* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */ -#define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */ -#define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */ -#define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */ -#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */ -#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */ +#define MICROCODEBASE 0x400 /* Microcode data base address */ +#define A_MICROCODEBASE 0x600 -/* Audigy Soundcard have a different instruction format */ -#define A_MICROCODEBASE 0x600 -#define A_LOWORD_OPY_MASK 0x000007ff -#define A_LOWORD_OPX_MASK 0x007ff000 -#define A_HIWORD_OPCODE_MASK 0x0f000000 -#define A_HIWORD_RESULT_MASK 0x007ff000 -#define A_HIWORD_OPA_MASK 0x000007ff +/************************************************************************************************/ +/* E-MU Digital Audio System overview */ +/************************************************************************************************/ + +// - These cards use a regular PCI-attached Audigy chip (Alice2/Tina/Tina2); +// the PCIe variants simply put the Audigy chip behind a PCI bridge. +// - All physical PCM I/O is routed through an additional FPGA; the regular +// EXTIN/EXTOUT ports are unconnected. +// - The FPGA has a signal routing matrix, to connect each destination (output +// socket or capture channel) to a source (input socket or playback channel). +// - The FPGA is controlled via Audigy's GPIO port, while sample data is +// transmitted via proprietary EMU32 serial links. On first-generation +// E-MU 1010 cards, Audigy's I2S inputs are also used for sample data. +// - The Audio/Micro Dock is attached to Hana via EDI, a "network" link. +// - The Audigy chip operates in slave mode; the clock is supplied by the FPGA. +// Gen1 E-MU 1010 cards have two crystals (for 44.1 kHz and 48 kHz multiples), +// while the later cards use a single crystal and a PLL chip. +// - The whole card is switched to 2x/4x mode to achieve 88.2/96/176.4/192 kHz +// sample rates. Alice2/Tina keeps running at 44.1/48 kHz, but multiple channels +// are bundled. +// - The number of available EMU32/EDI channels is hit in 2x/4x mode, so the total +// number of usable inputs/outputs is limited, esp. with ADAT in use. +// - S/PDIF is unavailable in 4x mode (only over TOSLINK on newer 1010 cards) due +// to being unspecified at 176.4/192 kHz. Therefore, the Dock's S/PDIF channels +// can overlap with the Dock's ADC/DAC's high channels. +// - The code names are mentioned below and in the emu_chip_details table. /************************************************************************************************/ -/* EMU1010m HANA FPGA registers */ +/* EMU1010 FPGA registers */ /************************************************************************************************/ + #define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */ #define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */ + #define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */ #define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */ + #define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */ #define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */ + #define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */ /* Must be written after power on to reset DLL */ /* One is unable to detect the Audio dock without this */ @@ -967,7 +985,7 @@ #define EMU_HANA_WCLOCK_INT_44_1K 0x01 #define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02 #define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03 -#define EMU_HANA_WCLOCK_SYNC_BNCN 0x04 +#define EMU_HANA_WCLOCK_SYNC_BNC 0x04 #define EMU_HANA_WCLOCK_2ND_HANA 0x05 #define EMU_HANA_WCLOCK_SRC_RESERVED 0x06 #define EMU_HANA_WCLOCK_OFF 0x07 /* For testing, forces fallback to DEFCLOCK */ @@ -977,6 +995,9 @@ #define EMU_HANA_WCLOCK_4X 0x10 #define EMU_HANA_WCLOCK_MULT_RESERVED 0x18 +// If the selected external clock source is/becomes invalid or incompatible +// with the clock multiplier, the clock source is reset to this value, and +// a WCLK_CHANGED interrupt is raised. #define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */ #define EMU_HANA_DEFCLOCK_48K 0x00 #define EMU_HANA_DEFCLOCK_44_1K 0x01 @@ -996,10 +1017,10 @@ #define EMU_HANA_IRQ_DOCK_LOST 0x08 #define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */ -#define EMU_HANA_SPDIF_MODE_TX_COMSUMER 0x00 +#define EMU_HANA_SPDIF_MODE_TX_CONSUMER 0x00 #define EMU_HANA_SPDIF_MODE_TX_PRO 0x01 #define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02 -#define EMU_HANA_SPDIF_MODE_RX_COMSUMER 0x00 +#define EMU_HANA_SPDIF_MODE_RX_CONSUMER 0x00 #define EMU_HANA_SPDIF_MODE_RX_PRO 0x04 #define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08 #define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10 @@ -1011,8 +1032,12 @@ #define EMU_HANA_OPTICAL_OUT_ADAT 0x02 #define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */ -#define EMU_HANA_MIDI_IN_FROM_HAMOA 0x00 /* HAMOA MIDI in to Alice 2 MIDI B */ -#define EMU_HANA_MIDI_IN_FROM_DOCK 0x01 /* Audio Dock MIDI in to Alice 2 MIDI B */ +#define EMU_HANA_MIDI_INA_FROM_HAMOA 0x01 /* HAMOA MIDI in to Alice 2 MIDI A */ +#define EMU_HANA_MIDI_INA_FROM_DOCK1 0x02 /* Audio Dock-1 MIDI in to Alice 2 MIDI A */ +#define EMU_HANA_MIDI_INA_FROM_DOCK2 0x03 /* Audio Dock-2 MIDI in to Alice 2 MIDI A */ +#define EMU_HANA_MIDI_INB_FROM_HAMOA 0x08 /* HAMOA MIDI in to Alice 2 MIDI B */ +#define EMU_HANA_MIDI_INB_FROM_DOCK1 0x10 /* Audio Dock-1 MIDI in to Alice 2 MIDI B */ +#define EMU_HANA_MIDI_INB_FROM_DOCK2 0x18 /* Audio Dock-2 MIDI in to Alice 2 MIDI B */ #define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */ #define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */ @@ -1037,51 +1062,49 @@ #define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */ #define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */ -#define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */ -#define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */ -#define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */ -#define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */ +#define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */ +#define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */ +#define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */ +#define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */ #define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */ -#define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */ -#define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */ -#define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */ -#define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */ +#define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */ +#define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */ +#define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */ +#define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */ #define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */ #define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */ #define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */ #define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */ #define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */ -#define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */ -#define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */ -#define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */ -#define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */ -#define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */ +#define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */ +#define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */ +#define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */ +#define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */ +#define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */ #define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */ -#define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */ -#define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */ -#define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */ -#define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */ -#define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */ +#define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */ +#define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */ +#define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */ +#define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */ +#define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */ /* 0x14 - 0x1f Unused R/W registers */ -#define EMU_HANA_IRQ_STATUS 0x20 /* 000xxxx 4 bits IRQ Status */ -#if 0 /* Already defined for reg 0x09 IRQ_ENABLE */ -#define EMU_HANA_IRQ_WCLK_CHANGED 0x01 -#define EMU_HANA_IRQ_ADAT 0x02 -#define EMU_HANA_IRQ_DOCK 0x04 -#define EMU_HANA_IRQ_DOCK_LOST 0x08 -#endif + +#define EMU_HANA_IRQ_STATUS 0x20 /* 00xxxxx 5 bits IRQ Status */ + /* Same bits as for EMU_HANA_IRQ_ENABLE */ + /* Reading the register resets it. */ #define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */ -#define EMU_HANA_OPTION_HAMOA 0x01 /* HAMOA card present */ -#define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */ -#define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio Dock online and FPGA configured */ -#define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio Dock online and FPGA not configured */ +#define EMU_HANA_OPTION_HAMOA 0x01 /* Hamoa (analog I/O) card present */ +#define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */ +#define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio/Micro dock present and FPGA configured */ +#define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio/Micro dock present and FPGA not configured */ -#define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 */ +#define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 with Alice2 */ + /* 0010101 5 bits ID byte & 0x1f = 0x15 with Tina/2 */ #define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */ #define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */ @@ -1090,8 +1113,11 @@ #define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */ #define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */ -#define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */ -#define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */ +#define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */ +#define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */ + +// The actual code disagrees about the bit width of the registers - +// the formula used is freq = 0x1770000 / (((X_HI << 5) | X_LO) + 1) #define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */ #define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */ @@ -1104,31 +1130,35 @@ #define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */ #define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */ + /* 0x30 - 0x3f Unused Read only registers */ +// The meaning of this is not clear; kX-project just calls it "lock" in some info-only code. +#define EMU_HANA_LOCK_STS_LO 0x38 /* 0xxxxxx lower 6 bits */ +#define EMU_HANA_LOCK_STS_HI 0x39 /* 0xxxxxx upper 6 bits */ + /************************************************************************************************/ -/* EMU1010m HANA Destinations */ +/* EMU1010 Audio Destinations */ /************************************************************************************************/ -/* Hana, original 1010,1212,1820 using Alice2 - * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz +/* Hana, original 1010,1212m,1820[m] using Alice2 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2 - * 0x01, 0x10-0x1f: 32 Elink channels to Audio Dock - * 0x01, 0x00: Dock DAC 1 Left - * 0x01, 0x04: Dock DAC 1 Right - * 0x01, 0x08: Dock DAC 2 Left - * 0x01, 0x0c: Dock DAC 2 Right - * 0x01, 0x10: Dock DAC 3 Left - * 0x01, 0x12: PHONES Left - * 0x01, 0x14: Dock DAC 3 Right - * 0x01, 0x16: PHONES Right - * 0x01, 0x18: Dock DAC 4 Left - * 0x01, 0x1a: S/PDIF Left - * 0x01, 0x1c: Dock DAC 4 Right - * 0x01, 0x1e: S/PDIF Right + * 0x01, 0x00-0x1f: 32 EDI channels to Audio Dock + * 0x00: Dock DAC 1 Left + * 0x04: Dock DAC 1 Right + * 0x08: Dock DAC 2 Left + * 0x0c: Dock DAC 2 Right + * 0x10: Dock DAC 3 Left + * 0x12: PHONES Left (n/a in 2x/4x mode; output mirrors DAC4 Left) + * 0x14: Dock DAC 3 Right + * 0x16: PHONES Right (n/a in 2x/4x mode; output mirrors DAC4 Right) + * 0x18: Dock DAC 4 Left + * 0x1a: S/PDIF Left + * 0x1c: Dock DAC 4 Right + * 0x1e: S/PDIF Right * 0x02, 0x00: Hana S/PDIF Left * 0x02, 0x01: Hana S/PDIF Right - * 0x03, 0x00: Hanoa DAC Left - * 0x03, 0x01: Hanoa DAC Right + * 0x03, 0x00: Hamoa DAC Left + * 0x03, 0x01: Hamoa DAC Right * 0x04, 0x00-0x07: Hana ADAT * 0x05, 0x00: I2S0 Left to Alice2 * 0x05, 0x01: I2S0 Right to Alice2 @@ -1140,40 +1170,29 @@ * Hana2 never released, but used Tina * Not needed. * - * Hana3, rev2 1010,1212,1616 using Tina - * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz + * Hana3, rev2 1010,1212m,1616[m] using Tina * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina - * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock - * 0x01, 0x00: Dock DAC 1 Left - * 0x01, 0x04: Dock DAC 1 Right - * 0x01, 0x08: Dock DAC 2 Left - * 0x01, 0x0c: Dock DAC 2 Right - * 0x01, 0x10: Dock DAC 3 Left - * 0x01, 0x12: Dock S/PDIF Left - * 0x01, 0x14: Dock DAC 3 Right - * 0x01, 0x16: Dock S/PDIF Right - * 0x01, 0x18-0x1f: Dock ADAT 0-7 + * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock + * 0x00: Dock DAC 1 Left + * 0x04: Dock DAC 1 Right + * 0x08: Dock DAC 2 Left + * 0x0c: Dock DAC 2 Right + * 0x10: Dock DAC 3 Left + * 0x12: Dock S/PDIF Left + * 0x14: Dock DAC 3 Right + * 0x16: Dock S/PDIF Right + * 0x18-0x1f: Dock ADAT 0-7 * 0x02, 0x00: Hana3 S/PDIF Left * 0x02, 0x01: Hana3 S/PDIF Right - * 0x03, 0x00: Hanoa DAC Left - * 0x03, 0x01: Hanoa DAC Right + * 0x03, 0x00: Hamoa DAC Left + * 0x03, 0x01: Hamoa DAC Right * 0x04, 0x00-0x07: Hana3 ADAT 0-7 * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina * 0x06-0x07: Not used * * HanaLite, rev1 0404 using Alice2 - * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz - * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2 - * 0x01: Not used - * 0x02, 0x00: S/PDIF Left - * 0x02, 0x01: S/PDIF Right - * 0x03, 0x00: DAC Left - * 0x03, 0x01: DAC Right - * 0x04-0x07: Not used - * - * HanaLiteLite, rev2 0404 using Alice2 - * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz - * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2 + * HanaLiteLite, rev2 0404 using Tina + * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2/Tina * 0x01: Not used * 0x02, 0x00: S/PDIF Left * 0x02, 0x01: S/PDIF Right @@ -1182,37 +1201,24 @@ * 0x04-0x07: Not used * * Mana, Cardbus 1616 using Tina2 - * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2 - * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock - * 0x01, 0x00: Dock DAC 1 Left - * 0x01, 0x04: Dock DAC 1 Right - * 0x01, 0x08: Dock DAC 2 Left - * 0x01, 0x0c: Dock DAC 2 Right - * 0x01, 0x10: Dock DAC 3 Left - * 0x01, 0x12: Dock S/PDIF Left - * 0x01, 0x14: Dock DAC 3 Right - * 0x01, 0x16: Dock S/PDIF Right - * 0x01, 0x18-0x1f: Dock ADAT 0-7 + * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock + * (same as rev2 1010) * 0x02: Not used * 0x03, 0x00: Mana DAC Left * 0x03, 0x01: Mana DAC Right * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2 * 0x05-0x07: Not used - * - * */ + /* 32-bit destinations of signal in the Hana FPGA. Destinations are either - * physical outputs of Hana, or outputs going to Alice2 (audigy) for capture - * - 16 x EMU_DST_ALICE2_EMU32_X. - */ -/* EMU32 = 32-bit serial channel between Alice2 (audigy) and Hana (FPGA) */ -/* EMU_DST_ALICE2_EMU32_X - data channels from Hana to Alice2 used for capture. - * Which data is fed into a EMU_DST_ALICE2_EMU32_X channel in Hana depends on - * setup of mixer control for each destination - see emumixer.c - - * snd_emu1010_output_enum_ctls[], snd_emu1010_input_enum_ctls[] + * physical outputs of Hana, or outputs going to Alice2/Tina for capture - + * 16 x EMU_DST_ALICE2_EMU32_X (2x on rev2 boards). Which data is fed into + * a channel depends on the mixer control setting for each destination - see + * the register arrays in emumixer.c. */ #define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */ + /* This channel is delayed by one sample. */ #define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */ #define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */ #define EMU_DST_ALICE2_EMU32_3 0x0002 /* 16 EMU32 channels to Alice2 +0 to +0xf */ @@ -1270,8 +1276,12 @@ #define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f /* Audio Dock SPDIF Right, 2nd or 96kHz */ #define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */ #define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */ +#define EMU_DST_HANA_SPDIF_LEFT3 0x0204 /* Hana SPDIF Left, 3rd or 192kHz */ +#define EMU_DST_HANA_SPDIF_LEFT4 0x0206 /* Hana SPDIF Left, 4th or 192kHz */ #define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */ #define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */ +#define EMU_DST_HANA_SPDIF_RIGHT3 0x0205 /* Hana SPDIF Right, 3rd or 192kHz */ +#define EMU_DST_HANA_SPDIF_RIGHT4 0x0207 /* Hana SPDIF Right, 4th or 192kHz */ #define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */ #define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */ #define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */ @@ -1280,6 +1290,7 @@ #define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */ #define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */ #define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */ +// In S/MUX mode, the samples of one channel are adjacent. #define EMU_DST_HANA_ADAT 0x0400 /* Hana ADAT 8 channel out +0 to +7 */ #define EMU_DST_ALICE_I2S0_LEFT 0x0500 /* Alice2 I2S0 Left */ #define EMU_DST_ALICE_I2S0_RIGHT 0x0501 /* Alice2 I2S0 Right */ @@ -1289,39 +1300,32 @@ #define EMU_DST_ALICE_I2S2_RIGHT 0x0701 /* Alice2 I2S2 Right */ /* Additional destinations for 1616(M)/Microdock */ -/* Microdock S/PDIF OUT Left, 1st or 48kHz only */ -#define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112 -/* Microdock S/PDIF OUT Left, 2nd or 96kHz */ -#define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113 -/* Microdock S/PDIF OUT Right, 1st or 48kHz only */ -#define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116 -/* Microdock S/PDIF OUT Right, 2nd or 96kHz */ -#define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117 -/* Microdock S/PDIF ADAT 8 channel out +8 to +f */ -#define EMU_DST_MDOCK_ADAT 0x0118 - -/* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ -#define EMU_DST_MANA_DAC_LEFT 0x0300 -/* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ -#define EMU_DST_MANA_DAC_RIGHT 0x0301 + +#define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */ +#define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */ +#define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */ +#define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF OUT Right, 2nd or 96kHz */ +#define EMU_DST_MDOCK_ADAT 0x0118 /* Microdock S/PDIF ADAT 8 channel out +8 to +f */ + +#define EMU_DST_MANA_DAC_LEFT 0x0300 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ +#define EMU_DST_MANA_DAC_RIGHT 0x0301 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ /************************************************************************************************/ -/* EMU1010m HANA Sources */ +/* EMU1010 Audio Sources */ /************************************************************************************************/ -/* Hana, original 1010,1212,1820 using Alice2 - * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz - * 0x00,0x00-0x1f: Silence - * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock - * 0x01, 0x00: Dock Mic A - * 0x01, 0x04: Dock Mic B - * 0x01, 0x08: Dock ADC 1 Left - * 0x01, 0x0c: Dock ADC 1 Right - * 0x01, 0x10: Dock ADC 2 Left - * 0x01, 0x14: Dock ADC 2 Right - * 0x01, 0x18: Dock ADC 3 Left - * 0x01, 0x1c: Dock ADC 3 Right - * 0x02, 0x00: Hana ADC Left - * 0x02, 0x01: Hana ADC Right +/* Hana, original 1010,1212m,1820[m] using Alice2 + * 0x00, 0x00-0x1f: Silence + * 0x01, 0x00-0x1f: 32 EDI channels from Audio Dock + * 0x00: Dock Mic A + * 0x04: Dock Mic B + * 0x08: Dock ADC 1 Left + * 0x0c: Dock ADC 1 Right + * 0x10: Dock ADC 2 Left + * 0x14: Dock ADC 2 Right + * 0x18: Dock ADC 3 Left + * 0x1c: Dock ADC 3 Right + * 0x02, 0x00: Hamoa ADC Left + * 0x02, 0x01: Hamoa ADC Right * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output * 0x04, 0x00-0x07: Hana ADAT @@ -1332,23 +1336,20 @@ * Hana2 never released, but used Tina * Not needed. * - * Hana3, rev2 1010,1212,1616 using Tina - * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz - * 0x00,0x00-0x1f: Silence - * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock - * 0x01, 0x00: Dock Mic A - * 0x01, 0x04: Dock Mic B - * 0x01, 0x08: Dock ADC 1 Left - * 0x01, 0x0c: Dock ADC 1 Right - * 0x01, 0x10: Dock ADC 2 Left - * 0x01, 0x12: Dock S/PDIF Left - * 0x01, 0x14: Dock ADC 2 Right - * 0x01, 0x16: Dock S/PDIF Right - * 0x01, 0x18-0x1f: Dock ADAT 0-7 - * 0x01, 0x18: Dock ADC 3 Left - * 0x01, 0x1c: Dock ADC 3 Right - * 0x02, 0x00: Hanoa ADC Left - * 0x02, 0x01: Hanoa ADC Right + * Hana3, rev2 1010,1212m,1616[m] using Tina + * 0x00, 0x00-0x1f: Silence + * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock + * 0x00: Dock Mic A + * 0x04: Dock Mic B + * 0x08: Dock ADC 1 Left + * 0x0c: Dock ADC 1 Right + * 0x10: Dock ADC 2 Left + * 0x12: Dock S/PDIF Left + * 0x14: Dock ADC 2 Right + * 0x16: Dock S/PDIF Right + * 0x18-0x1f: Dock ADAT 0-7 + * 0x02, 0x00: Hamoa ADC Left + * 0x02, 0x01: Hamoa ADC Right * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output * 0x04, 0x00-0x07: Hana3 ADAT @@ -1357,58 +1358,32 @@ * 0x06-0x07: Not used * * HanaLite, rev1 0404 using Alice2 - * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz - * 0x00,0x00-0x1f: Silence + * HanaLiteLite, rev2 0404 using Tina + * 0x00, 0x00-0x1f: Silence * 0x01: Not used * 0x02, 0x00: ADC Left * 0x02, 0x01: ADC Right - * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output - * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output - * 0x04: Not used - * 0x05, 0x00: S/PDIF Left - * 0x05, 0x01: S/PDIF Right - * 0x06-0x07: Not used - * - * HanaLiteLite, rev2 0404 using Alice2 - * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz - * 0x00,0x00-0x1f: Silence - * 0x01: Not used - * 0x02, 0x00: ADC Left - * 0x02, 0x01: ADC Right - * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output - * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output + * 0x03, 0x00-0x0f: 16 inputs from Alice2/Tina Emu32A output + * 0x03, 0x10-0x1f: 16 inputs from Alice2/Tina Emu32B output * 0x04: Not used * 0x05, 0x00: S/PDIF Left * 0x05, 0x01: S/PDIF Right * 0x06-0x07: Not used * * Mana, Cardbus 1616 using Tina2 - * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz - * 0x00,0x00-0x1f: Silence - * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock - * 0x01, 0x00: Dock Mic A - * 0x01, 0x04: Dock Mic B - * 0x01, 0x08: Dock ADC 1 Left - * 0x01, 0x0c: Dock ADC 1 Right - * 0x01, 0x10: Dock ADC 2 Left - * 0x01, 0x12: Dock S/PDIF Left - * 0x01, 0x14: Dock ADC 2 Right - * 0x01, 0x16: Dock S/PDIF Right - * 0x01, 0x18-0x1f: Dock ADAT 0-7 - * 0x01, 0x18: Dock ADC 3 Left - * 0x01, 0x1c: Dock ADC 3 Right + * 0x00, 0x00-0x1f: Silence + * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock + * (same as rev2 1010) * 0x02: Not used - * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output - * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output + * 0x03, 0x00-0x0f: 16 inputs from Tina2 Emu32A output + * 0x03, 0x10-0x1f: 16 inputs from Tina2 Emu32B output * 0x04-0x07: Not used - * */ /* 32-bit sources of signal in the Hana FPGA. The sources are routed to - * destinations using mixer control for each destination - see emumixer.c - * Sources are either physical inputs of FPGA, - * or outputs from Alice (audigy) - 16 x EMU_SRC_ALICE_EMU32A + - * 16 x EMU_SRC_ALICE_EMU32B + * destinations using a mixer control for each destination - see emumixer.c. + * Sources are either physical inputs of Hana, or inputs from Alice2/Tina - + * 16 x EMU_SRC_ALICE_EMU32A + 16 x EMU_SRC_ALICE_EMU32B. */ #define EMU_SRC_SILENCE 0x0000 /* Silence */ #define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */ @@ -1453,45 +1428,56 @@ #define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */ #define EMU_SRC_ALICE_EMU32A 0x0300 /* Alice2 EMU32a 16 outputs. +0 to +0xf */ #define EMU_SRC_ALICE_EMU32B 0x0310 /* Alice2 EMU32b 16 outputs. +0 to +0xf */ +// In S/MUX mode, the samples of one channel are adjacent. #define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */ #define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */ #define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */ +#define EMU_SRC_HANA_SPDIF_LEFT3 0x0504 /* Hana SPDIF Left, 3rd or 192kHz */ +#define EMU_SRC_HANA_SPDIF_LEFT4 0x0506 /* Hana SPDIF Left, 4th or 192kHz */ #define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */ #define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */ +#define EMU_SRC_HANA_SPDIF_RIGHT3 0x0505 /* Hana SPDIF Right, 3rd or 192kHz */ +#define EMU_SRC_HANA_SPDIF_RIGHT4 0x0507 /* Hana SPDIF Right, 4th or 192kHz */ /* Additional inputs for 1616(M)/Microdock */ -/* Microdock S/PDIF Left, 1st or 48kHz only */ -#define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112 -/* Microdock S/PDIF Left, 2nd or 96kHz */ -#define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113 -/* Microdock S/PDIF Right, 1st or 48kHz only */ -#define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116 -/* Microdock S/PDIF Right, 2nd or 96kHz */ -#define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117 -/* Microdock ADAT 8 channel in +8 to +f */ -#define EMU_SRC_MDOCK_ADAT 0x0118 + +#define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF Left, 1st or 48kHz only */ +#define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF Left, 2nd or 96kHz */ +#define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF Right, 1st or 48kHz only */ +#define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF Right, 2nd or 96kHz */ +#define EMU_SRC_MDOCK_ADAT 0x0118 /* Microdock ADAT 8 channel in +8 to +f */ /* 0x600 and 0x700 no used */ + +/* ------------------- CONSTANTS -------------------- */ + +extern const char * const snd_emu10k1_fxbus[32]; +extern const char * const snd_emu10k1_sblive_ins[16]; +extern const char * const snd_emu10k1_audigy_ins[16]; +extern const char * const snd_emu10k1_sblive_outs[32]; +extern const char * const snd_emu10k1_audigy_outs[32]; +extern const s8 snd_emu10k1_sblive51_fxbus2_map[16]; + /* ------------------- STRUCTURES -------------------- */ enum { + EMU10K1_UNUSED, // This must be zero EMU10K1_EFX, + EMU10K1_EFX_IRQ, EMU10K1_PCM, + EMU10K1_PCM_IRQ, EMU10K1_SYNTH, - EMU10K1_MIDI + EMU10K1_NUM_TYPES }; struct snd_emu10k1; struct snd_emu10k1_voice { - struct snd_emu10k1 *emu; - int number; - unsigned int use: 1, - pcm: 1, - efx: 1, - synth: 1, - midi: 1; + unsigned char number; + unsigned char use; + unsigned char dirty; + unsigned char last; void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice); struct snd_emu10k1_pcm *epcm; @@ -1513,7 +1499,9 @@ struct snd_emu10k1_pcm { struct snd_emu10k1_voice *extra; unsigned short running; unsigned short first_ptr; + snd_pcm_uframes_t resume_pos; struct snd_util_memblk *memblk; + unsigned int pitch_target; unsigned int start_addr; unsigned int ccca_start_addr; unsigned int capture_ipr; /* interrupt acknowledge mask */ @@ -1531,6 +1519,8 @@ struct snd_emu10k1_pcm_mixer { /* mono, left, right x 8 sends (4 on emu10k1) */ unsigned char send_routing[3][8]; unsigned char send_volume[3][8]; + // 0x8000 is neutral. The mixer code rescales it to 0xffff to maintain + // backwards compatibility with user space. unsigned short attn[3]; struct snd_emu10k1_pcm *epcm; }; @@ -1539,10 +1529,13 @@ struct snd_emu10k1_pcm_mixer { ((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16) #define snd_emu10k1_compose_audigy_fxrt1(route) \ -((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24)) +((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24) | 0x80808080) #define snd_emu10k1_compose_audigy_fxrt2(route) \ -((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24)) +((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24) | 0x80808080) + +#define snd_emu10k1_compose_audigy_sendamounts(vol) \ +(((unsigned int)vol[4] << 24) | ((unsigned int)vol[5] << 16) | ((unsigned int)vol[6] << 8) | (unsigned int)vol[7]) struct snd_emu10k1_memblk { struct snd_util_memblk mem; @@ -1562,9 +1555,9 @@ struct snd_emu10k1_fx8010_ctl { unsigned int vcount; unsigned int count; /* count of GPR (1..16) */ unsigned short gpr[32]; /* GPR number(s) */ - unsigned int value[32]; - unsigned int min; /* minimum range */ - unsigned int max; /* maximum range */ + int value[32]; + int min; /* minimum range */ + int max; /* maximum range */ unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ struct snd_kcontrol *kcontrol; }; @@ -1599,10 +1592,8 @@ struct snd_emu10k1_fx8010_pcm { }; struct snd_emu10k1_fx8010 { - unsigned short fxbus_mask; /* used FX buses (bitmask) */ - unsigned short extin_mask; /* used external inputs (bitmask) */ - unsigned short extout_mask; /* used external outputs (bitmask) */ - unsigned short pad1; + unsigned short extin_mask; /* used external inputs (bitmask); not used for Audigy */ + unsigned short extout_mask; /* used external outputs (bitmask); not used for Audigy */ unsigned int itram_size; /* internal TRAM size in samples */ struct snd_dma_buffer etram_pages; /* external TRAM pages and size */ unsigned int dbg; /* FX debugger register */ @@ -1639,42 +1630,62 @@ enum { EMU_MODEL_EMU0404, }; +// Chip-o-logy: +// - All SB Live! cards use EMU10K1 chips +// - All SB Audigy cards use CA* chips, termed "emu10k2" by the driver +// - Original Audigy uses CA0100 "Alice" +// - Audigy 2 uses CA0102/CA10200 "Alice2" +// - Has an interface for CA0151 (P16V) "Alice3" +// - Audigy 2 Value uses CA0108/CA10300 "Tina" +// - Approximately a CA0102 with an on-chip CA0151 (P17V) +// - Audigy 2 ZS NB uses CA0109 "Tina2" +// - Cardbus version of CA0108 struct snd_emu_chip_details { u32 vendor; u32 device; u32 subsystem; unsigned char revision; - unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */ - unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */ - unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */ - unsigned char ca0108_chip; /* Audigy 2 Value */ - unsigned char ca_cardbus_chip; /* Audigy 2 ZS Notebook */ - unsigned char ca0151_chip; /* P16V */ - unsigned char spk71; /* Has 7.1 speakers */ - unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */ - unsigned char spdif_bug; /* Has Spdif phasing bug */ - unsigned char ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */ - unsigned char ecard; /* APS EEPROM */ - unsigned char emu_model; /* EMU model type */ - unsigned char spi_dac; /* SPI interface for DAC */ - unsigned char i2c_adc; /* I2C interface for ADC */ - unsigned char adc_1361t; /* Use Philips 1361T ADC */ - unsigned char invert_shared_spdif; /* analog/digital switch inverted */ + unsigned char emu_model; /* EMU model type */ + unsigned int emu10k1_chip:1; /* Original SB Live. Not SB Live 24bit. */ + /* Redundant with emu10k2_chip being unset. */ + unsigned int emu10k2_chip:1; /* Audigy 1 or Audigy 2. */ + unsigned int ca0102_chip:1; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */ + /* Redundant with ca0108_chip being unset. */ + unsigned int ca0108_chip:1; /* Audigy 2 Value */ + unsigned int ca_cardbus_chip:1; /* Audigy 2 ZS Notebook */ + unsigned int ca0151_chip:1; /* P16V */ + unsigned int spk20:1; /* Stereo only */ + unsigned int spk71:1; /* Has 7.1 speakers */ + unsigned int no_adat:1; /* Has no ADAT, only SPDIF */ + unsigned int sblive51:1; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */ + unsigned int spdif_bug:1; /* Has Spdif phasing bug */ + unsigned int ac97_chip:2; /* Has an AC97 chip: 1 = mandatory, 2 = optional */ + unsigned int ecard:1; /* APS EEPROM */ + unsigned int spi_dac:1; /* SPI interface for DAC; requires ca0108_chip */ + unsigned int i2c_adc:1; /* I2C interface for ADC; requires ca0108_chip */ + unsigned int adc_1361t:1; /* Use Philips 1361T ADC */ + unsigned int invert_shared_spdif:1; /* analog/digital switch inverted */ const char *driver; const char *name; const char *id; /* for backward compatibility - can be NULL if not needed */ }; +#define NUM_OUTPUT_DESTS 28 +#define NUM_INPUT_DESTS 22 + struct snd_emu1010 { - unsigned int output_source[64]; - unsigned int input_source[64]; + unsigned char output_source[NUM_OUTPUT_DESTS]; + unsigned char input_source[NUM_INPUT_DESTS]; unsigned int adc_pads; /* bit mask */ unsigned int dac_pads; /* bit mask */ - unsigned int internal_clock; /* 44100 or 48000 */ + unsigned int wclock; /* Cached register value */ + unsigned int word_clock; /* Cached effective value */ + unsigned int clock_source; + unsigned int clock_fallback; unsigned int optical_in; /* 0:SPDIF, 1:ADAT */ unsigned int optical_out; /* 0:SPDIF, 1:ADAT */ - struct delayed_work firmware_work; - u32 last_reg; + struct work_struct firmware_work; + struct work_struct clock_work; }; struct snd_emu10k1 { @@ -1691,12 +1702,10 @@ struct snd_emu10k1 { unsigned int revision; /* chip revision */ unsigned int serial; /* serial number */ unsigned short model; /* subsystem id */ - unsigned int card_type; /* EMU10K1_CARD_* */ unsigned int ecard_ctrl; /* ecard control bits */ unsigned int address_mode; /* address mode */ unsigned long dma_mask; /* PCI DMA mask */ bool iommu_workaround; /* IOMMU workaround needed */ - unsigned int delay_pcm_irq; /* in samples */ int max_cache_pages; /* max memory size / PAGE_SIZE */ struct snd_dma_buffer silent_page; /* silent page */ struct snd_dma_buffer ptb_pages; /* page table pages */ @@ -1732,15 +1741,13 @@ struct snd_emu10k1 { void *synth; int (*get_synth_voice)(struct snd_emu10k1 *emu); - spinlock_t reg_lock; - spinlock_t emu_lock; - spinlock_t voice_lock; + spinlock_t reg_lock; // high-level driver lock + spinlock_t emu_lock; // low-level i/o lock + spinlock_t voice_lock; // voice allocator lock spinlock_t spi_lock; /* serialises access to spi port */ spinlock_t i2c_lock; /* serialises access to i2c port */ struct snd_emu10k1_voice voices[NUM_G]; - struct snd_emu10k1_voice p16v_voices[4]; - struct snd_emu10k1_voice p16v_capture_voice; int p16v_device_offset; u32 p16v_capture_source; u32 p16v_capture_channel; @@ -1753,6 +1760,7 @@ struct snd_emu10k1 { struct snd_kcontrol *ctl_efx_send_routing; struct snd_kcontrol *ctl_efx_send_volume; struct snd_kcontrol *ctl_efx_attn; + struct snd_kcontrol *ctl_clock_source; void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status); void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status); @@ -1760,11 +1768,12 @@ struct snd_emu10k1 { void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status); void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status); void (*dsp_interrupt)(struct snd_emu10k1 *emu); + void (*gpio_interrupt)(struct snd_emu10k1 *emu); + void (*p16v_interrupt)(struct snd_emu10k1 *emu); struct snd_pcm_substream *pcm_capture_substream; struct snd_pcm_substream *pcm_capture_mic_substream; struct snd_pcm_substream *pcm_capture_efx_substream; - struct snd_pcm_substream *pcm_playback_efx_substream; struct snd_timer *timer; @@ -1820,13 +1829,17 @@ int snd_emu10k1_done(struct snd_emu10k1 * emu); /* I/O functions */ unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); +void snd_emu10k1_ptr_write_multiple(struct snd_emu10k1 *emu, unsigned int chn, ...); unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data); int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value); -int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, u32 reg, u32 value); -int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, u32 reg, u32 *value); -int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, u32 dst, u32 src); +void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value); +void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value); +void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src); +u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst); +int snd_emu1010_get_raw_rate(struct snd_emu10k1 *emu, u8 src); +void snd_emu1010_update_clock(struct snd_emu10k1 *emu); unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc); void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb); void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb); @@ -1836,13 +1849,17 @@ void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum); void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum); void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum); void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum); +#if 0 void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum); void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum); +#endif +void snd_emu10k1_voice_set_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices); +void snd_emu10k1_voice_clear_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices); +int snd_emu10k1_voice_clear_loop_stop_multiple_atomic(struct snd_emu10k1 *emu, u64 voices); void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait); static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; } unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg); void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data); -unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate); #ifdef CONFIG_PM_SLEEP void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu); @@ -1870,7 +1887,8 @@ int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_me int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk); /* voice allocation */ -int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int pair, struct snd_emu10k1_voice **rvoice); +int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int count, int channels, + struct snd_emu10k1_pcm *epcm, struct snd_emu10k1_voice **rvoice); int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice); /* MIDI uart */ diff --git a/include/sound/emux_synth.h b/include/sound/emux_synth.h index d499b68122a3..1cc530434b97 100644 --- a/include/sound/emux_synth.h +++ b/include/sound/emux_synth.h @@ -54,6 +54,7 @@ struct snd_emux_operators { #if IS_ENABLED(CONFIG_SND_SEQUENCER_OSS) int (*oss_ioctl)(struct snd_emux *emu, int cmd, int p1, int p2); #endif + int (*get_pitch_shift)(struct snd_emux *emu); }; @@ -82,7 +83,6 @@ struct snd_emux { int max_voices; /* Number of voices */ int mem_size; /* memory size (in byte) */ int num_ports; /* number of ports to be created */ - int pitch_shift; /* pitch shift value (for Emu10k1) */ struct snd_emux_operators ops; /* operators */ void *hw; /* hardware */ unsigned long flags; /* other conditions */ diff --git a/include/sound/hda-mlink.h b/include/sound/hda-mlink.h new file mode 100644 index 000000000000..228114aca415 --- /dev/null +++ b/include/sound/hda-mlink.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2022-2023 Intel Corporation. All rights reserved. + */ + +struct hdac_bus; +struct hdac_ext_link; + +#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_MLINK) + +int hda_bus_ml_init(struct hdac_bus *bus); +void hda_bus_ml_free(struct hdac_bus *bus); + +int hdac_bus_eml_get_count(struct hdac_bus *bus, bool alt, int elid); +void hdac_bus_eml_enable_interrupt(struct hdac_bus *bus, bool alt, int elid, bool enable); +bool hdac_bus_eml_check_interrupt(struct hdac_bus *bus, bool alt, int elid); + +int hdac_bus_eml_set_syncprd_unlocked(struct hdac_bus *bus, bool alt, int elid, u32 syncprd); +int hdac_bus_eml_sdw_set_syncprd_unlocked(struct hdac_bus *bus, u32 syncprd); + +int hdac_bus_eml_wait_syncpu_unlocked(struct hdac_bus *bus, bool alt, int elid); +int hdac_bus_eml_sdw_wait_syncpu_unlocked(struct hdac_bus *bus); + +void hdac_bus_eml_sync_arm_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink); +void hdac_bus_eml_sdw_sync_arm_unlocked(struct hdac_bus *bus, int sublink); + +int hdac_bus_eml_sync_go_unlocked(struct hdac_bus *bus, bool alt, int elid); +int hdac_bus_eml_sdw_sync_go_unlocked(struct hdac_bus *bus); + +bool hdac_bus_eml_check_cmdsync_unlocked(struct hdac_bus *bus, bool alt, int elid); +bool hdac_bus_eml_sdw_check_cmdsync_unlocked(struct hdac_bus *bus); + +int hdac_bus_eml_power_up(struct hdac_bus *bus, bool alt, int elid, int sublink); +int hdac_bus_eml_power_up_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink); + +int hdac_bus_eml_power_down(struct hdac_bus *bus, bool alt, int elid, int sublink); +int hdac_bus_eml_power_down_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink); + +int hdac_bus_eml_sdw_power_up_unlocked(struct hdac_bus *bus, int sublink); +int hdac_bus_eml_sdw_power_down_unlocked(struct hdac_bus *bus, int sublink); + +int hdac_bus_eml_sdw_get_lsdiid_unlocked(struct hdac_bus *bus, int sublink, u16 *lsdiid); +int hdac_bus_eml_sdw_set_lsdiid(struct hdac_bus *bus, int sublink, int dev_num); + +int hdac_bus_eml_sdw_map_stream_ch(struct hdac_bus *bus, int sublink, int y, + int channel_mask, int stream_id, int dir); + +void hda_bus_ml_put_all(struct hdac_bus *bus); +void hda_bus_ml_reset_losidv(struct hdac_bus *bus); +int hda_bus_ml_resume(struct hdac_bus *bus); +int hda_bus_ml_suspend(struct hdac_bus *bus); + +struct hdac_ext_link *hdac_bus_eml_ssp_get_hlink(struct hdac_bus *bus); +struct hdac_ext_link *hdac_bus_eml_dmic_get_hlink(struct hdac_bus *bus); +struct hdac_ext_link *hdac_bus_eml_sdw_get_hlink(struct hdac_bus *bus); + +struct mutex *hdac_bus_eml_get_mutex(struct hdac_bus *bus, bool alt, int elid); + +int hdac_bus_eml_enable_offload(struct hdac_bus *bus, bool alt, int elid, bool enable); + +#else + +static inline int +hda_bus_ml_init(struct hdac_bus *bus) { return 0; } + +static inline void hda_bus_ml_free(struct hdac_bus *bus) { } + +static inline int +hdac_bus_eml_get_count(struct hdac_bus *bus, bool alt, int elid) { return 0; } + +static inline void +hdac_bus_eml_enable_interrupt(struct hdac_bus *bus, bool alt, int elid, bool enable) { } + +static inline bool +hdac_bus_eml_check_interrupt(struct hdac_bus *bus, bool alt, int elid) { return false; } + +static inline int +hdac_bus_eml_set_syncprd_unlocked(struct hdac_bus *bus, bool alt, int elid, u32 syncprd) +{ + return 0; +} + +static inline int +hdac_bus_eml_sdw_set_syncprd_unlocked(struct hdac_bus *bus, u32 syncprd) +{ + return 0; +} + +static inline int +hdac_bus_eml_wait_syncpu_unlocked(struct hdac_bus *bus, bool alt, int elid) +{ + return 0; +} + +static inline int +hdac_bus_eml_sdw_wait_syncpu_unlocked(struct hdac_bus *bus) { return 0; } + +static inline void +hdac_bus_eml_sync_arm_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink) { } + +static inline void +hdac_bus_eml_sdw_sync_arm_unlocked(struct hdac_bus *bus, int sublink) { } + +static inline int +hdac_bus_eml_sync_go_unlocked(struct hdac_bus *bus, bool alt, int elid) { return 0; } + +static inline int +hdac_bus_eml_sdw_sync_go_unlocked(struct hdac_bus *bus) { return 0; } + +static inline bool +hdac_bus_eml_check_cmdsync_unlocked(struct hdac_bus *bus, bool alt, int elid) { return false; } + +static inline bool +hdac_bus_eml_sdw_check_cmdsync_unlocked(struct hdac_bus *bus) { return false; } + +static inline int +hdac_bus_eml_power_up(struct hdac_bus *bus, bool alt, int elid, int sublink) +{ + return 0; +} + +static inline int +hdac_bus_eml_power_up_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink) +{ + return 0; +} + +static inline int +hdac_bus_eml_power_down(struct hdac_bus *bus, bool alt, int elid, int sublink) +{ + return 0; +} + +static inline int +hdac_bus_eml_power_down_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink) +{ + return 0; +} + +static inline int +hdac_bus_eml_sdw_power_up_unlocked(struct hdac_bus *bus, int sublink) { return 0; } + +static inline int +hdac_bus_eml_sdw_power_down_unlocked(struct hdac_bus *bus, int sublink) { return 0; } + +static inline int +hdac_bus_eml_sdw_get_lsdiid_unlocked(struct hdac_bus *bus, int sublink, u16 *lsdiid) { return 0; } + +static inline int +hdac_bus_eml_sdw_set_lsdiid(struct hdac_bus *bus, int sublink, int dev_num) { return 0; } + +static inline int +hdac_bus_eml_sdw_map_stream_ch(struct hdac_bus *bus, int sublink, int y, + int channel_mask, int stream_id, int dir) +{ + return 0; +} + +static inline void hda_bus_ml_put_all(struct hdac_bus *bus) { } +static inline void hda_bus_ml_reset_losidv(struct hdac_bus *bus) { } +static inline int hda_bus_ml_resume(struct hdac_bus *bus) { return 0; } +static inline int hda_bus_ml_suspend(struct hdac_bus *bus) { return 0; } + +static inline struct hdac_ext_link * +hdac_bus_eml_ssp_get_hlink(struct hdac_bus *bus) { return NULL; } + +static inline struct hdac_ext_link * +hdac_bus_eml_dmic_get_hlink(struct hdac_bus *bus) { return NULL; } + +static inline struct hdac_ext_link * +hdac_bus_eml_sdw_get_hlink(struct hdac_bus *bus) { return NULL; } + +static inline struct mutex * +hdac_bus_eml_get_mutex(struct hdac_bus *bus, bool alt, int elid) { return NULL; } + +static inline int +hdac_bus_eml_enable_offload(struct hdac_bus *bus, bool alt, int elid, bool enable) +{ + return 0; +} +#endif /* CONFIG_SND_SOC_SOF_HDA */ diff --git a/include/sound/hda_codec.h b/include/sound/hda_codec.h index bbb7805e85d8..5497dc9c396a 100644 --- a/include/sound/hda_codec.h +++ b/include/sound/hda_codec.h @@ -18,9 +18,6 @@ #include <sound/hda_verbs.h> #include <sound/hda_regmap.h> -#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) -#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348) - /* * Structures */ diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h index d37cf43546eb..9c7872c0ca79 100644 --- a/include/sound/hda_register.h +++ b/include/sound/hda_register.h @@ -258,14 +258,27 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define AZX_ML_BASE 0x40 #define AZX_ML_INTERVAL 0x40 +/* HDaudio registers valid for HDaudio and HDaudio extended links */ #define AZX_REG_ML_LCAP 0x00 -#define AZX_REG_ML_LCTL 0x04 +#define AZX_ML_HDA_LCAP_ALT BIT(28) +#define AZX_ML_HDA_LCAP_ALT_HDA 0x0 +#define AZX_ML_HDA_LCAP_ALT_HDA_EXT 0x1 + +#define AZX_ML_HDA_LCAP_INTC BIT(27) /* only used if ALT == 1 */ +#define AZX_ML_HDA_LCAP_OFLS BIT(26) /* only used if ALT == 1 */ +#define AZX_ML_HDA_LCAP_LSS BIT(23) /* only used if ALT == 1 */ +#define AZX_ML_HDA_LCAP_SLCOUNT GENMASK(22, 20) /* only used if ALT == 1 */ + +#define AZX_REG_ML_LCTL 0x04 +#define AZX_ML_LCTL_INTSTS BIT(31) /* only used if ALT == 1 */ #define AZX_ML_LCTL_CPA BIT(23) #define AZX_ML_LCTL_CPA_SHIFT 23 #define AZX_ML_LCTL_SPA BIT(16) #define AZX_ML_LCTL_SPA_SHIFT 16 -#define AZX_ML_LCTL_SCF GENMASK(3, 0) +#define AZX_ML_LCTL_INTEN BIT(5) /* only used if ALT == 1 */ +#define AZX_ML_LCTL_OFLEN BIT(4) /* only used if ALT == 1 */ +#define AZX_ML_LCTL_SCF GENMASK(3, 0) /* only used if ALT == 0 */ #define AZX_REG_ML_LOSIDV 0x08 @@ -273,12 +286,35 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define AZX_ML_LOSIDV_STREAM_MASK 0xFFFE #define AZX_REG_ML_LSDIID 0x0C +#define AZX_REG_ML_LSDIID_OFFSET(x) (0x0C + (x) * 0x02) /* only used if ALT == 1 */ + +/* HDaudio registers only valid if LCAP.ALT == 0 */ #define AZX_REG_ML_LPSOO 0x10 #define AZX_REG_ML_LPSIO 0x12 #define AZX_REG_ML_LWALFC 0x18 #define AZX_REG_ML_LOUTPAY 0x20 #define AZX_REG_ML_LINPAY 0x30 +/* HDaudio Extended link registers only valid if LCAP.ALT == 1 */ +#define AZX_REG_ML_LSYNC 0x1C + +#define AZX_REG_ML_LSYNC_CMDSYNC BIT(24) +#define AZX_REG_ML_LSYNC_CMDSYNC_SHIFT 24 +#define AZX_REG_ML_LSYNC_SYNCGO BIT(23) +#define AZX_REG_ML_LSYNC_SYNCPU BIT(20) +#define AZX_REG_ML_LSYNC_SYNCPRD GENMASK(19, 0) + +#define AZX_REG_ML_LEPTR 0x20 + +#define AZX_REG_ML_LEPTR_ID GENMASK(31, 24) +#define AZX_REG_ML_LEPTR_ID_SHIFT 24 +#define AZX_REG_ML_LEPTR_ID_SDW 0x00 +#define AZX_REG_ML_LEPTR_ID_INTEL_SSP 0xC0 +#define AZX_REG_ML_LEPTR_ID_INTEL_DMIC 0xC1 +#define AZX_REG_ML_LEPTR_ID_INTEL_UAOL 0xC2 +#define AZX_REG_ML_LEPTR_VER GENMASK(23, 20) +#define AZX_REG_ML_LEPTR_PTR GENMASK(19, 0) + /* registers for DMA Resume Capability Structure */ #define AZX_DRSM_CAP_ID 0x5 #define AZX_REG_DRSM_CTL 0x4 diff --git a/include/sound/hdaudio.h b/include/sound/hdaudio.h index 97f09acae302..32c59053b48e 100644 --- a/include/sound/hdaudio.h +++ b/include/sound/hdaudio.h @@ -11,6 +11,7 @@ #include <linux/io.h> #include <linux/io-64-nonatomic-lo-hi.h> #include <linux/iopoll.h> +#include <linux/pci.h> #include <linux/pm_runtime.h> #include <linux/timecounter.h> #include <sound/core.h> @@ -347,6 +348,8 @@ struct hdac_bus { bool corbrp_self_clear:1; /* CORBRP clears itself after reset */ bool polling_mode:1; bool needs_damn_long_delay:1; + bool not_use_interrupts:1; /* prohibiting the RIRB IRQ */ + bool access_sdnctl_in_dword:1; /* accessing the sdnctl register by dword */ int poll_count; @@ -702,4 +705,29 @@ static inline unsigned int snd_array_index(struct snd_array *array, void *ptr) for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \ (ptr) = snd_array_elem(array, ++(idx))) +/* + * Device matching + */ + +#define HDA_CONTROLLER_IS_HSW(pci) (pci_match_id((struct pci_device_id []){ \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_0) }, \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_2) }, \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_3) }, \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_BDW) }, \ + { } \ + }, pci)) + +#define HDA_CONTROLLER_IS_APL(pci) (pci_match_id((struct pci_device_id []){ \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_APL) }, \ + { } \ + }, pci)) + +#define HDA_CONTROLLER_IN_GPU(pci) (pci_match_id((struct pci_device_id []){ \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG1) }, \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_0) }, \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_1) }, \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_2) }, \ + { } \ + }, pci) || HDA_CONTROLLER_IS_HSW(pci)) + #endif /* __SOUND_HDAUDIO_H */ diff --git a/include/sound/hwdep.h b/include/sound/hwdep.h index 8d6cdb254039..b0da633184cd 100644 --- a/include/sound/hwdep.h +++ b/include/sound/hwdep.h @@ -53,7 +53,7 @@ struct snd_hwdep { wait_queue_head_t open_wait; void *private_data; void (*private_free) (struct snd_hwdep *hwdep); - struct device dev; + struct device *dev; struct mutex open_mutex; int used; /* reference counter */ diff --git a/include/sound/info.h b/include/sound/info.h index 7c13bf52cc81..adbc506860d6 100644 --- a/include/sound/info.h +++ b/include/sound/info.h @@ -118,8 +118,6 @@ struct snd_info_entry *snd_info_create_card_entry(struct snd_card *card, const char *name, struct snd_info_entry *parent); void snd_info_free_entry(struct snd_info_entry *entry); -int snd_info_store_text(struct snd_info_entry *entry); -int snd_info_restore_text(struct snd_info_entry *entry); int snd_info_card_create(struct snd_card *card); int snd_info_card_register(struct snd_card *card); diff --git a/include/sound/l3.h b/include/sound/l3.h deleted file mode 100644 index b6f58072237a..000000000000 --- a/include/sound/l3.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _L3_H_ -#define _L3_H_ 1 - -struct l3_pins { - void (*setdat)(struct l3_pins *, int); - void (*setclk)(struct l3_pins *, int); - void (*setmode)(struct l3_pins *, int); - - int gpio_data; - int gpio_clk; - int gpio_mode; - int use_gpios; - - int data_hold; - int data_setup; - int clock_high; - int mode_hold; - int mode; - int mode_setup; -}; - -struct device; - -int l3_write(struct l3_pins *adap, u8 addr, u8 *data, int len); -int l3_set_gpio_ops(struct device *dev, struct l3_pins *adap); - -#endif diff --git a/include/sound/pcm-indirect.h b/include/sound/pcm-indirect.h index 04127686e8d0..98e06ea73b2b 100644 --- a/include/sound/pcm-indirect.h +++ b/include/sound/pcm-indirect.h @@ -44,7 +44,7 @@ snd_pcm_indirect_playback_transfer(struct snd_pcm_substream *substream, if (diff < -(snd_pcm_sframes_t) (runtime->boundary / 2)) diff += runtime->boundary; if (diff < 0) - return -EINVAL; + return -EPIPE; rec->sw_ready += (int)frames_to_bytes(runtime, diff); rec->appl_ptr = appl_ptr; } @@ -83,6 +83,8 @@ snd_pcm_indirect_playback_pointer(struct snd_pcm_substream *substream, struct snd_pcm_indirect *rec, unsigned int ptr) { int bytes = ptr - rec->hw_io; + int err; + if (bytes < 0) bytes += rec->hw_buffer_size; rec->hw_io = ptr; @@ -90,8 +92,11 @@ snd_pcm_indirect_playback_pointer(struct snd_pcm_substream *substream, rec->sw_io += bytes; if (rec->sw_io >= rec->sw_buffer_size) rec->sw_io -= rec->sw_buffer_size; - if (substream->ops->ack) - substream->ops->ack(substream); + if (substream->ops->ack) { + err = substream->ops->ack(substream); + if (err == -EPIPE) + return SNDRV_PCM_POS_XRUN; + } return bytes_to_frames(substream->runtime, rec->sw_io); } @@ -112,7 +117,7 @@ snd_pcm_indirect_capture_transfer(struct snd_pcm_substream *substream, if (diff < -(snd_pcm_sframes_t) (runtime->boundary / 2)) diff += runtime->boundary; if (diff < 0) - return -EINVAL; + return -EPIPE; rec->sw_ready -= frames_to_bytes(runtime, diff); rec->appl_ptr = appl_ptr; } @@ -152,6 +157,8 @@ snd_pcm_indirect_capture_pointer(struct snd_pcm_substream *substream, { int qsize; int bytes = ptr - rec->hw_io; + int err; + if (bytes < 0) bytes += rec->hw_buffer_size; rec->hw_io = ptr; @@ -162,8 +169,11 @@ snd_pcm_indirect_capture_pointer(struct snd_pcm_substream *substream, rec->sw_io += bytes; if (rec->sw_io >= rec->sw_buffer_size) rec->sw_io -= rec->sw_buffer_size; - if (substream->ops->ack) - substream->ops->ack(substream); + if (substream->ops->ack) { + err = substream->ops->ack(substream); + if (err == -EPIPE) + return SNDRV_PCM_POS_XRUN; + } return bytes_to_frames(substream->runtime, rec->sw_io); } diff --git a/include/sound/pcm.h b/include/sound/pcm.h index 27040b472a4f..2a815373dac1 100644 --- a/include/sound/pcm.h +++ b/include/sound/pcm.h @@ -16,6 +16,7 @@ #include <linux/bitops.h> #include <linux/pm_qos.h> #include <linux/refcount.h> +#include <linux/uio.h> #define snd_pcm_substream_chip(substream) ((substream)->private_data) #define snd_pcm_chip(pcm) ((pcm)->private_data) @@ -68,11 +69,8 @@ struct snd_pcm_ops { struct snd_pcm_audio_tstamp_report *audio_tstamp_report); int (*fill_silence)(struct snd_pcm_substream *substream, int channel, unsigned long pos, unsigned long bytes); - int (*copy_user)(struct snd_pcm_substream *substream, int channel, - unsigned long pos, void __user *buf, - unsigned long bytes); - int (*copy_kernel)(struct snd_pcm_substream *substream, int channel, - unsigned long pos, void *buf, unsigned long bytes); + int (*copy)(struct snd_pcm_substream *substream, int channel, + unsigned long pos, struct iov_iter *iter, unsigned long bytes); struct page *(*page)(struct snd_pcm_substream *substream, unsigned long offset); int (*mmap)(struct snd_pcm_substream *substream, struct vm_area_struct *vma); @@ -378,18 +376,18 @@ struct snd_pcm_runtime { unsigned int rate_den; unsigned int no_period_wakeup: 1; - /* -- SW params -- */ - int tstamp_mode; /* mmap timestamp is updated */ + /* -- SW params; see struct snd_pcm_sw_params for comments -- */ + int tstamp_mode; unsigned int period_step; snd_pcm_uframes_t start_threshold; snd_pcm_uframes_t stop_threshold; - snd_pcm_uframes_t silence_threshold; /* Silence filling happens when - noise is nearest than this */ - snd_pcm_uframes_t silence_size; /* Silence filling size */ - snd_pcm_uframes_t boundary; /* pointers wrap point */ + snd_pcm_uframes_t silence_threshold; + snd_pcm_uframes_t silence_size; + snd_pcm_uframes_t boundary; + /* internal data of auto-silencer */ snd_pcm_uframes_t silence_start; /* starting pointer to silence area */ - snd_pcm_uframes_t silence_filled; /* size filled with silence */ + snd_pcm_uframes_t silence_filled; /* already filled part of silence area */ union snd_pcm_sync_id sync; /* hardware synchronization ID */ @@ -510,7 +508,7 @@ struct snd_pcm_str { #endif #endif struct snd_kcontrol *chmap_kctl; /* channel-mapping controls */ - struct device dev; + struct device *dev; }; struct snd_pcm { @@ -1556,6 +1554,11 @@ static inline u64 pcm_format_to_bits(snd_pcm_format_t pcm_format) #define pcm_dbg(pcm, fmt, args...) \ dev_dbg((pcm)->card->dev, fmt, ##args) +/* helpers for copying between iov_iter and iomem */ +int copy_to_iter_fromio(struct iov_iter *itert, const void __iomem *src, + size_t count); +int copy_from_iter_toio(void __iomem *dst, struct iov_iter *iter, size_t count); + struct snd_pcm_status64 { snd_pcm_state_t state; /* stream state */ u8 rsvd[4]; diff --git a/include/sound/rawmidi.h b/include/sound/rawmidi.h index e1f59b2940af..f31cabf0158c 100644 --- a/include/sound/rawmidi.h +++ b/include/sound/rawmidi.h @@ -18,6 +18,7 @@ #if IS_ENABLED(CONFIG_SND_SEQUENCER) #include <sound/seq_device.h> #endif +#include <sound/info.h> /* * Raw MIDI interface @@ -47,6 +48,10 @@ struct snd_rawmidi_global_ops { int (*dev_unregister) (struct snd_rawmidi * rmidi); void (*get_port_info)(struct snd_rawmidi *rmidi, int number, struct snd_seq_port_info *info); + long (*ioctl)(struct snd_rawmidi *rmidi, unsigned int cmd, + void __user *argp); + void (*proc_read)(struct snd_info_entry *entry, + struct snd_info_buffer *buf); }; struct snd_rawmidi_runtime { @@ -61,6 +66,7 @@ struct snd_rawmidi_runtime { size_t avail_min; /* min avail for wakeup */ size_t avail; /* max used buffer for wakeup */ size_t xruns; /* over/underruns counter */ + size_t align; /* alignment (0 = byte stream, 3 = UMP) */ int buffer_ref; /* buffer reference count */ /* misc */ wait_queue_head_t sleep; @@ -129,7 +135,7 @@ struct snd_rawmidi { struct mutex open_mutex; wait_queue_head_t open_wait; - struct device dev; + struct device *dev; struct snd_info_entry *proc_entry; @@ -146,6 +152,13 @@ int snd_rawmidi_new(struct snd_card *card, char *id, int device, void snd_rawmidi_set_ops(struct snd_rawmidi *rmidi, int stream, const struct snd_rawmidi_ops *ops); +/* internal */ +int snd_rawmidi_init(struct snd_rawmidi *rmidi, + struct snd_card *card, char *id, int device, + int output_count, int input_count, + unsigned int info_flags); +int snd_rawmidi_free(struct snd_rawmidi *rmidi); + /* callbacks */ int snd_rawmidi_receive(struct snd_rawmidi_substream *substream, @@ -161,7 +174,7 @@ int snd_rawmidi_proceed(struct snd_rawmidi_substream *substream); /* main midi functions */ int snd_rawmidi_info_select(struct snd_card *card, struct snd_rawmidi_info *info); -int snd_rawmidi_kernel_open(struct snd_card *card, int device, int subdevice, +int snd_rawmidi_kernel_open(struct snd_rawmidi *rmidi, int subdevice, int mode, struct snd_rawmidi_file *rfile); int snd_rawmidi_kernel_release(struct snd_rawmidi_file *rfile); int snd_rawmidi_output_params(struct snd_rawmidi_substream *substream, diff --git a/include/sound/rt5665.h b/include/sound/rt5665.h index 3b3d6a19ca49..e865f041929b 100644 --- a/include/sound/rt5665.h +++ b/include/sound/rt5665.h @@ -31,8 +31,6 @@ struct rt5665_platform_data { bool in3_diff; bool in4_diff; - int ldo1_en; /* GPIO for LDO1_EN */ - enum rt5665_dmic1_data_pin dmic1_data_pin; enum rt5665_dmic2_data_pin dmic2_data_pin; enum rt5665_jd_src jd_src; diff --git a/include/sound/rt5668.h b/include/sound/rt5668.h index 182edfbc9e7a..b682418c6cd6 100644 --- a/include/sound/rt5668.h +++ b/include/sound/rt5668.h @@ -25,9 +25,6 @@ enum rt5668_jd_src { }; struct rt5668_platform_data { - - int ldo1_en; /* GPIO for LDO1_EN */ - enum rt5668_dmic1_data_pin dmic1_data_pin; enum rt5668_dmic1_clk_pin dmic1_clk_pin; enum rt5668_jd_src jd_src; diff --git a/include/sound/rt5682.h b/include/sound/rt5682.h index 3900a07e3935..4256df721e3a 100644 --- a/include/sound/rt5682.h +++ b/include/sound/rt5682.h @@ -31,9 +31,6 @@ enum rt5682_dai_clks { }; struct rt5682_platform_data { - - int ldo1_en; /* GPIO for LDO1_EN */ - enum rt5682_dmic1_data_pin dmic1_data_pin; enum rt5682_dmic1_clk_pin dmic1_clk_pin; enum rt5682_jd_src jd_src; diff --git a/include/sound/rt5682s.h b/include/sound/rt5682s.h index f18d91308b9a..66ca0c75b914 100644 --- a/include/sound/rt5682s.h +++ b/include/sound/rt5682s.h @@ -32,9 +32,6 @@ enum rt5682s_dai_clks { }; struct rt5682s_platform_data { - - int ldo1_en; /* GPIO for LDO1_EN */ - enum rt5682s_dmic1_data_pin dmic1_data_pin; enum rt5682s_dmic1_clk_pin dmic1_clk_pin; enum rt5682s_jd_src jd_src; diff --git a/include/sound/seq_device.h b/include/sound/seq_device.h index 8899affe9155..dead74b022f4 100644 --- a/include/sound/seq_device.h +++ b/include/sound/seq_device.h @@ -78,5 +78,6 @@ void snd_seq_driver_unregister(struct snd_seq_driver *drv); */ #define SNDRV_SEQ_DEV_ID_MIDISYNTH "seq-midi" #define SNDRV_SEQ_DEV_ID_OPL3 "opl3-synth" +#define SNDRV_SEQ_DEV_ID_UMP "seq-ump-client" #endif /* __SOUND_SEQ_DEVICE_H */ diff --git a/include/sound/seq_kernel.h b/include/sound/seq_kernel.h index 658911926f3a..c8621671fa70 100644 --- a/include/sound/seq_kernel.h +++ b/include/sound/seq_kernel.h @@ -70,9 +70,19 @@ int snd_seq_kernel_client_ctl(int client, unsigned int cmd, void *arg); typedef int (*snd_seq_dump_func_t)(void *ptr, void *buf, int count); int snd_seq_expand_var_event(const struct snd_seq_event *event, int count, char *buf, int in_kernel, int size_aligned); +int snd_seq_expand_var_event_at(const struct snd_seq_event *event, int count, + char *buf, int offset); int snd_seq_dump_var_event(const struct snd_seq_event *event, snd_seq_dump_func_t func, void *private_data); +/* size of the event packet; it can be greater than snd_seq_event size */ +static inline size_t snd_seq_event_packet_size(struct snd_seq_event *ev) +{ + if (snd_seq_ev_is_ump(ev)) + return sizeof(struct snd_seq_ump_event); + return sizeof(struct snd_seq_event); +} + /* interface for OSS emulation */ int snd_seq_set_queue_tempo(int client, struct snd_seq_queue_tempo *tempo); diff --git a/include/sound/simple_card_utils.h b/include/sound/simple_card_utils.h index a3f3f3aa9e6e..d1a95bc33c56 100644 --- a/include/sound/simple_card_utils.h +++ b/include/sound/simple_card_utils.h @@ -59,9 +59,6 @@ struct asoc_simple_priv { struct simple_dai_props { struct asoc_simple_dai *cpu_dai; struct asoc_simple_dai *codec_dai; - struct snd_soc_dai_link_component *cpus; - struct snd_soc_dai_link_component *codecs; - struct snd_soc_dai_link_component *platforms; struct asoc_simple_data adata; struct snd_soc_codec_conf *codec_conf; struct prop_nums num; @@ -73,7 +70,6 @@ struct asoc_simple_priv { struct snd_soc_dai_link *dai_link; struct asoc_simple_dai *dais; struct snd_soc_dai_link_component *dlcs; - struct snd_soc_dai_link_component dummy; struct snd_soc_codec_conf *codec_conf; struct gpio_desc *pa_gpio; const struct snd_soc_ops *ops; @@ -196,6 +192,8 @@ int asoc_simple_remove(struct platform_device *pdev); int asoc_graph_card_probe(struct snd_soc_card *card); int asoc_graph_is_ports0(struct device_node *port); +int asoc_graph_parse_dai(struct device *dev, struct device_node *ep, + struct snd_soc_dai_link_component *dlc, int *is_single_link); #ifdef DEBUG static inline void asoc_simple_debug_dai(struct asoc_simple_priv *priv, diff --git a/include/sound/soc-acpi-intel-match.h b/include/sound/soc-acpi-intel-match.h index 82a7db23db69..e49b97d9e3ff 100644 --- a/include/sound/soc-acpi-intel-match.h +++ b/include/sound/soc-acpi-intel-match.h @@ -31,6 +31,7 @@ extern struct snd_soc_acpi_mach snd_soc_acpi_intel_jsl_machines[]; extern struct snd_soc_acpi_mach snd_soc_acpi_intel_adl_machines[]; extern struct snd_soc_acpi_mach snd_soc_acpi_intel_rpl_machines[]; extern struct snd_soc_acpi_mach snd_soc_acpi_intel_mtl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_lnl_machines[]; extern struct snd_soc_acpi_mach snd_soc_acpi_intel_cnl_sdw_machines[]; extern struct snd_soc_acpi_mach snd_soc_acpi_intel_cfl_sdw_machines[]; @@ -40,6 +41,7 @@ extern struct snd_soc_acpi_mach snd_soc_acpi_intel_tgl_sdw_machines[]; extern struct snd_soc_acpi_mach snd_soc_acpi_intel_adl_sdw_machines[]; extern struct snd_soc_acpi_mach snd_soc_acpi_intel_rpl_sdw_machines[]; extern struct snd_soc_acpi_mach snd_soc_acpi_intel_mtl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_lnl_sdw_machines[]; /* * generic table used for HDA codec-based platforms, possibly with diff --git a/include/sound/soc-acpi.h b/include/sound/soc-acpi.h index b38fd25c5729..6d31d535e8f6 100644 --- a/include/sound/soc-acpi.h +++ b/include/sound/soc-acpi.h @@ -9,6 +9,7 @@ #include <linux/stddef.h> #include <linux/acpi.h> #include <linux/mod_devicetable.h> +#include <linux/soundwire/sdw.h> struct snd_soc_acpi_package_context { char *name; /* package name */ @@ -150,6 +151,7 @@ struct snd_soc_acpi_link_adr { * all firmware/topology related fields. * * @id: ACPI ID (usually the codec's) used to find a matching machine driver. + * @uid: ACPI Unique ID, can be used to disambiguate matches. * @comp_ids: list of compatible audio codecs using the same machine driver, * firmware and topology * @link_mask: describes required board layout, e.g. for SoundWire. @@ -170,6 +172,7 @@ struct snd_soc_acpi_link_adr { /* Descriptor for SST ASoC machine driver */ struct snd_soc_acpi_mach { u8 id[ACPI_ID_LEN]; + const char *uid; const struct snd_soc_acpi_codecs *comp_ids; const u32 link_mask; const struct snd_soc_acpi_link_adr *links; @@ -207,4 +210,9 @@ static inline bool snd_soc_acpi_sof_parent(struct device *dev) !strncmp(dev->parent->driver->name, "sof-audio-acpi", strlen("sof-audio-acpi")); } +bool snd_soc_acpi_sdw_link_slaves_found(struct device *dev, + const struct snd_soc_acpi_link_adr *link, + struct sdw_extended_slave_id *ids, + int num_slaves); + #endif diff --git a/include/sound/soc-card.h b/include/sound/soc-card.h index 9d31a5c0db33..fc94dfb0021f 100644 --- a/include/sound/soc-card.h +++ b/include/sound/soc-card.h @@ -9,10 +9,25 @@ #define __SOC_CARD_H enum snd_soc_card_subclass { - SND_SOC_CARD_CLASS_INIT = 0, + SND_SOC_CARD_CLASS_ROOT = 0, SND_SOC_CARD_CLASS_RUNTIME = 1, }; +static inline void snd_soc_card_mutex_lock_root(struct snd_soc_card *card) +{ + mutex_lock_nested(&card->mutex, SND_SOC_CARD_CLASS_ROOT); +} + +static inline void snd_soc_card_mutex_lock(struct snd_soc_card *card) +{ + mutex_lock_nested(&card->mutex, SND_SOC_CARD_CLASS_RUNTIME); +} + +static inline void snd_soc_card_mutex_unlock(struct snd_soc_card *card) +{ + mutex_unlock(&card->mutex); +} + struct snd_kcontrol *snd_soc_card_get_kcontrol(struct snd_soc_card *soc_card, const char *name); int snd_soc_card_jack_new(struct snd_soc_card *card, const char *id, int type, diff --git a/include/sound/soc-component.h b/include/sound/soc-component.h index 0814ed143864..17bea3144551 100644 --- a/include/sound/soc-component.h +++ b/include/sound/soc-component.h @@ -137,10 +137,10 @@ struct snd_soc_component_driver { struct timespec64 *audio_ts, struct snd_pcm_audio_tstamp_config *audio_tstamp_config, struct snd_pcm_audio_tstamp_report *audio_tstamp_report); - int (*copy_user)(struct snd_soc_component *component, - struct snd_pcm_substream *substream, int channel, - unsigned long pos, void __user *buf, - unsigned long bytes); + int (*copy)(struct snd_soc_component *component, + struct snd_pcm_substream *substream, int channel, + unsigned long pos, struct iov_iter *buf, + unsigned long bytes); struct page *(*page)(struct snd_soc_component *component, struct snd_pcm_substream *substream, unsigned long offset); @@ -159,6 +159,15 @@ struct snd_soc_component_driver { int remove_order; /* + * soc_pcm_trigger() start/stop sequence. + * see also + * snd_soc_dai_link + * soc_pcm_trigger() + */ + enum snd_soc_trigger_order trigger_start; + enum snd_soc_trigger_order trigger_stop; + + /* * signal if the module handling the component should not be removed * if a pcm is open. Setting this would prevent the module * refcount being incremented in probe() but allow it be incremented @@ -190,8 +199,6 @@ struct snd_soc_component_driver { bool use_dai_pcm_id; /* use DAI link PCM ID as PCM device number */ int be_pcm_base; /* base device ID for all BE PCMs */ - unsigned int start_dma_last; - #ifdef CONFIG_DEBUG_FS const char *debugfs_prefix; #endif @@ -454,6 +461,10 @@ int snd_soc_component_force_enable_pin_unlocked( struct snd_soc_component *component, const char *pin); +/* component controls */ +int snd_soc_component_notify_control(struct snd_soc_component *component, + const char * const ctl); + /* component driver ops */ int snd_soc_component_open(struct snd_soc_component *component, struct snd_pcm_substream *substream); @@ -498,9 +509,9 @@ int snd_soc_pcm_component_pointer(struct snd_pcm_substream *substream); int snd_soc_pcm_component_ioctl(struct snd_pcm_substream *substream, unsigned int cmd, void *arg); int snd_soc_pcm_component_sync_stop(struct snd_pcm_substream *substream); -int snd_soc_pcm_component_copy_user(struct snd_pcm_substream *substream, - int channel, unsigned long pos, - void __user *buf, unsigned long bytes); +int snd_soc_pcm_component_copy(struct snd_pcm_substream *substream, + int channel, unsigned long pos, + struct iov_iter *buf, unsigned long bytes); struct page *snd_soc_pcm_component_page(struct snd_pcm_substream *substream, unsigned long offset); int snd_soc_pcm_component_mmap(struct snd_pcm_substream *substream, diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h index e3906ecda740..5fcfba47d98c 100644 --- a/include/sound/soc-dai.h +++ b/include/sound/soc-dai.h @@ -271,7 +271,18 @@ int snd_soc_dai_compr_get_metadata(struct snd_soc_dai *dai, struct snd_compr_stream *cstream, struct snd_compr_metadata *metadata); +const char *snd_soc_dai_name_get(struct snd_soc_dai *dai); + struct snd_soc_dai_ops { + /* DAI driver callbacks */ + int (*probe)(struct snd_soc_dai *dai); + int (*remove)(struct snd_soc_dai *dai); + /* compress dai */ + int (*compress_new)(struct snd_soc_pcm_runtime *rtd, int num); + /* Optional Callback used at pcm creation*/ + int (*pcm_new)(struct snd_soc_pcm_runtime *rtd, + struct snd_soc_dai *dai); + /* * DAI clocking configuration, all optional. * Called by soc_card drivers, normally in their hw_params. @@ -353,6 +364,10 @@ struct snd_soc_dai_ops { u64 *auto_selectable_formats; int num_auto_selectable_formats; + /* probe ordering - for components with runtime dependencies */ + int probe_order; + int remove_order; + /* bit field */ unsigned int no_capture_mute:1; }; @@ -397,15 +412,7 @@ struct snd_soc_dai_driver { unsigned int id; unsigned int base; struct snd_soc_dobj dobj; - - /* DAI driver callbacks */ - int (*probe)(struct snd_soc_dai *dai); - int (*remove)(struct snd_soc_dai *dai); - /* compress dai */ - int (*compress_new)(struct snd_soc_pcm_runtime *rtd, int num); - /* Optional Callback used at pcm creation*/ - int (*pcm_new)(struct snd_soc_pcm_runtime *rtd, - struct snd_soc_dai *dai); + struct of_phandle_args *dai_args; /* ops */ const struct snd_soc_dai_ops *ops; @@ -417,10 +424,6 @@ struct snd_soc_dai_driver { unsigned int symmetric_rate:1; unsigned int symmetric_channels:1; unsigned int symmetric_sample_bits:1; - - /* probe ordering - for components with runtime dependencies */ - int probe_order; - int remove_order; }; /* for Playback/Capture */ diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h index 64915ebd641e..d2faec9a323e 100644 --- a/include/sound/soc-dapm.h +++ b/include/sound/soc-dapm.h @@ -42,36 +42,45 @@ struct soc_enum; /* codec domain */ #define SND_SOC_DAPM_VMID(wname) \ -{ .id = snd_soc_dapm_vmid, .name = wname, .kcontrol_news = NULL, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_vmid, .name = wname, .kcontrol_news = NULL, \ .num_kcontrols = 0} /* platform domain */ #define SND_SOC_DAPM_SIGGEN(wname) \ -{ .id = snd_soc_dapm_siggen, .name = wname, .kcontrol_news = NULL, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_siggen, .name = wname, .kcontrol_news = NULL, \ .num_kcontrols = 0, .reg = SND_SOC_NOPM } #define SND_SOC_DAPM_SINK(wname) \ -{ .id = snd_soc_dapm_sink, .name = wname, .kcontrol_news = NULL, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_sink, .name = wname, .kcontrol_news = NULL, \ .num_kcontrols = 0, .reg = SND_SOC_NOPM } #define SND_SOC_DAPM_INPUT(wname) \ -{ .id = snd_soc_dapm_input, .name = wname, .kcontrol_news = NULL, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_input, .name = wname, .kcontrol_news = NULL, \ .num_kcontrols = 0, .reg = SND_SOC_NOPM } #define SND_SOC_DAPM_OUTPUT(wname) \ -{ .id = snd_soc_dapm_output, .name = wname, .kcontrol_news = NULL, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_output, .name = wname, .kcontrol_news = NULL, \ .num_kcontrols = 0, .reg = SND_SOC_NOPM } #define SND_SOC_DAPM_MIC(wname, wevent) \ -{ .id = snd_soc_dapm_mic, .name = wname, .kcontrol_news = NULL, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mic, .name = wname, .kcontrol_news = NULL, \ .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD} #define SND_SOC_DAPM_HP(wname, wevent) \ -{ .id = snd_soc_dapm_hp, .name = wname, .kcontrol_news = NULL, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_hp, .name = wname, .kcontrol_news = NULL, \ .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD} #define SND_SOC_DAPM_SPK(wname, wevent) \ -{ .id = snd_soc_dapm_spk, .name = wname, .kcontrol_news = NULL, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_spk, .name = wname, .kcontrol_news = NULL, \ .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD} #define SND_SOC_DAPM_LINE(wname, wevent) \ -{ .id = snd_soc_dapm_line, .name = wname, .kcontrol_news = NULL, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_line, .name = wname, .kcontrol_news = NULL, \ .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD} @@ -82,93 +91,110 @@ struct soc_enum; /* path domain */ #define SND_SOC_DAPM_PGA(wname, wreg, wshift, winvert,\ wcontrols, wncontrols) \ -{ .id = snd_soc_dapm_pga, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_pga, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = wncontrols} #define SND_SOC_DAPM_OUT_DRV(wname, wreg, wshift, winvert,\ wcontrols, wncontrols) \ -{ .id = snd_soc_dapm_out_drv, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_out_drv, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = wncontrols} #define SND_SOC_DAPM_MIXER(wname, wreg, wshift, winvert, \ wcontrols, wncontrols)\ -{ .id = snd_soc_dapm_mixer, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mixer, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = wncontrols} #define SND_SOC_DAPM_MIXER_NAMED_CTL(wname, wreg, wshift, winvert, \ wcontrols, wncontrols)\ -{ .id = snd_soc_dapm_mixer_named_ctl, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mixer_named_ctl, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = wncontrols} /* DEPRECATED: use SND_SOC_DAPM_SUPPLY */ #define SND_SOC_DAPM_MICBIAS(wname, wreg, wshift, winvert) \ -{ .id = snd_soc_dapm_micbias, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_micbias, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = NULL, .num_kcontrols = 0} #define SND_SOC_DAPM_SWITCH(wname, wreg, wshift, winvert, wcontrols) \ -{ .id = snd_soc_dapm_switch, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_switch, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = 1} #define SND_SOC_DAPM_MUX(wname, wreg, wshift, winvert, wcontrols) \ -{ .id = snd_soc_dapm_mux, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mux, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = 1} #define SND_SOC_DAPM_DEMUX(wname, wreg, wshift, winvert, wcontrols) \ -{ .id = snd_soc_dapm_demux, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_demux, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = 1} /* Simplified versions of above macros, assuming wncontrols = ARRAY_SIZE(wcontrols) */ #define SOC_PGA_ARRAY(wname, wreg, wshift, winvert,\ wcontrols) \ -{ .id = snd_soc_dapm_pga, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_pga, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols)} #define SOC_MIXER_ARRAY(wname, wreg, wshift, winvert, \ wcontrols)\ -{ .id = snd_soc_dapm_mixer, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mixer, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols)} #define SOC_MIXER_NAMED_CTL_ARRAY(wname, wreg, wshift, winvert, \ wcontrols)\ -{ .id = snd_soc_dapm_mixer_named_ctl, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mixer_named_ctl, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols)} /* path domain with event - event handler must return 0 for success */ #define SND_SOC_DAPM_PGA_E(wname, wreg, wshift, winvert, wcontrols, \ wncontrols, wevent, wflags) \ -{ .id = snd_soc_dapm_pga, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_pga, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = wncontrols, \ .event = wevent, .event_flags = wflags} #define SND_SOC_DAPM_OUT_DRV_E(wname, wreg, wshift, winvert, wcontrols, \ wncontrols, wevent, wflags) \ -{ .id = snd_soc_dapm_out_drv, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_out_drv, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = wncontrols, \ .event = wevent, .event_flags = wflags} #define SND_SOC_DAPM_MIXER_E(wname, wreg, wshift, winvert, wcontrols, \ wncontrols, wevent, wflags) \ -{ .id = snd_soc_dapm_mixer, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mixer, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = wncontrols, \ .event = wevent, .event_flags = wflags} #define SND_SOC_DAPM_MIXER_NAMED_CTL_E(wname, wreg, wshift, winvert, \ wcontrols, wncontrols, wevent, wflags) \ -{ .id = snd_soc_dapm_mixer, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mixer, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, \ .num_kcontrols = wncontrols, .event = wevent, .event_flags = wflags} #define SND_SOC_DAPM_SWITCH_E(wname, wreg, wshift, winvert, wcontrols, \ wevent, wflags) \ -{ .id = snd_soc_dapm_switch, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_switch, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = 1, \ .event = wevent, .event_flags = wflags} #define SND_SOC_DAPM_MUX_E(wname, wreg, wshift, winvert, wcontrols, \ wevent, wflags) \ -{ .id = snd_soc_dapm_mux, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mux, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = 1, \ .event = wevent, .event_flags = wflags} @@ -176,101 +202,121 @@ struct soc_enum; /* additional sequencing control within an event type */ #define SND_SOC_DAPM_PGA_S(wname, wsubseq, wreg, wshift, winvert, \ wevent, wflags) \ -{ .id = snd_soc_dapm_pga, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_pga, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .event = wevent, .event_flags = wflags, \ .subseq = wsubseq} #define SND_SOC_DAPM_SUPPLY_S(wname, wsubseq, wreg, wshift, winvert, wevent, \ wflags) \ -{ .id = snd_soc_dapm_supply, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_supply, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .event = wevent, .event_flags = wflags, .subseq = wsubseq} /* Simplified versions of above macros, assuming wncontrols = ARRAY_SIZE(wcontrols) */ #define SOC_PGA_E_ARRAY(wname, wreg, wshift, winvert, wcontrols, \ wevent, wflags) \ -{ .id = snd_soc_dapm_pga, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_pga, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols), \ .event = wevent, .event_flags = wflags} #define SOC_MIXER_E_ARRAY(wname, wreg, wshift, winvert, wcontrols, \ wevent, wflags) \ -{ .id = snd_soc_dapm_mixer, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mixer, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols), \ .event = wevent, .event_flags = wflags} #define SOC_MIXER_NAMED_CTL_E_ARRAY(wname, wreg, wshift, winvert, \ wcontrols, wevent, wflags) \ -{ .id = snd_soc_dapm_mixer, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mixer, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols), \ .event = wevent, .event_flags = wflags} /* events that are pre and post DAPM */ #define SND_SOC_DAPM_PRE(wname, wevent) \ -{ .id = snd_soc_dapm_pre, .name = wname, .kcontrol_news = NULL, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_pre, .name = wname, .kcontrol_news = NULL, \ .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD} #define SND_SOC_DAPM_POST(wname, wevent) \ -{ .id = snd_soc_dapm_post, .name = wname, .kcontrol_news = NULL, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_post, .name = wname, .kcontrol_news = NULL, \ .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD} /* stream domain */ #define SND_SOC_DAPM_AIF_IN(wname, stname, wchan, wreg, wshift, winvert) \ -{ .id = snd_soc_dapm_aif_in, .name = wname, .sname = stname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_aif_in, .name = wname, .sname = stname, \ .channel = wchan, SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), } #define SND_SOC_DAPM_AIF_IN_E(wname, stname, wchan, wreg, wshift, winvert, \ wevent, wflags) \ -{ .id = snd_soc_dapm_aif_in, .name = wname, .sname = stname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_aif_in, .name = wname, .sname = stname, \ .channel = wchan, SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .event = wevent, .event_flags = wflags } #define SND_SOC_DAPM_AIF_OUT(wname, stname, wchan, wreg, wshift, winvert) \ -{ .id = snd_soc_dapm_aif_out, .name = wname, .sname = stname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_aif_out, .name = wname, .sname = stname, \ .channel = wchan, SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), } #define SND_SOC_DAPM_AIF_OUT_E(wname, stname, wchan, wreg, wshift, winvert, \ wevent, wflags) \ -{ .id = snd_soc_dapm_aif_out, .name = wname, .sname = stname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_aif_out, .name = wname, .sname = stname, \ .channel = wchan, SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .event = wevent, .event_flags = wflags } #define SND_SOC_DAPM_DAC(wname, stname, wreg, wshift, winvert) \ -{ .id = snd_soc_dapm_dac, .name = wname, .sname = stname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_dac, .name = wname, .sname = stname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert) } #define SND_SOC_DAPM_DAC_E(wname, stname, wreg, wshift, winvert, \ wevent, wflags) \ -{ .id = snd_soc_dapm_dac, .name = wname, .sname = stname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_dac, .name = wname, .sname = stname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .event = wevent, .event_flags = wflags} #define SND_SOC_DAPM_ADC(wname, stname, wreg, wshift, winvert) \ -{ .id = snd_soc_dapm_adc, .name = wname, .sname = stname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_adc, .name = wname, .sname = stname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), } #define SND_SOC_DAPM_ADC_E(wname, stname, wreg, wshift, winvert, \ wevent, wflags) \ -{ .id = snd_soc_dapm_adc, .name = wname, .sname = stname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_adc, .name = wname, .sname = stname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .event = wevent, .event_flags = wflags} #define SND_SOC_DAPM_CLOCK_SUPPLY(wname) \ -{ .id = snd_soc_dapm_clock_supply, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_clock_supply, .name = wname, \ .reg = SND_SOC_NOPM, .event = dapm_clock_event, \ .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD } /* generic widgets */ #define SND_SOC_DAPM_REG(wid, wname, wreg, wshift, wmask, won_val, woff_val) \ -{ .id = wid, .name = wname, .kcontrol_news = NULL, .num_kcontrols = 0, \ +(struct snd_soc_dapm_widget) { \ + .id = wid, .name = wname, .kcontrol_news = NULL, .num_kcontrols = 0, \ .reg = wreg, .shift = wshift, .mask = wmask, \ .on_val = won_val, .off_val = woff_val, } #define SND_SOC_DAPM_SUPPLY(wname, wreg, wshift, winvert, wevent, wflags) \ -{ .id = snd_soc_dapm_supply, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_supply, .name = wname, \ SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ .event = wevent, .event_flags = wflags} #define SND_SOC_DAPM_REGULATOR_SUPPLY(wname, wdelay, wflags) \ -{ .id = snd_soc_dapm_regulator_supply, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_regulator_supply, .name = wname, \ .reg = SND_SOC_NOPM, .shift = wdelay, .event = dapm_regulator_event, \ .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD, \ .on_val = wflags} #define SND_SOC_DAPM_PINCTRL(wname, active, sleep) \ -{ .id = snd_soc_dapm_pinctrl, .name = wname, \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_pinctrl, .name = wname, \ .priv = (&(struct snd_soc_dapm_pinctrl_priv) \ { .active_state = active, .sleep_state = sleep,}), \ .reg = SND_SOC_NOPM, .event = dapm_pinctrl_event, \ @@ -527,11 +573,6 @@ enum snd_soc_dapm_type { SND_SOC_DAPM_TYPE_COUNT }; -enum snd_soc_dapm_subclass { - SND_SOC_DAPM_CLASS_INIT = 0, - SND_SOC_DAPM_CLASS_RUNTIME = 1, -}; - /* * DAPM audio route definition. * @@ -609,6 +650,7 @@ struct snd_soc_dapm_widget { unsigned char power_checked:1; /* power checked this run */ unsigned char is_supply:1; /* Widget is a supply type widget */ unsigned char is_ep:2; /* Widget is a endpoint type widget */ + unsigned char no_wname_in_kcontrol_name:1; /* No widget name prefix in kcontrol name */ int subseq; /* sort within widget type */ int (*power_check)(struct snd_soc_dapm_widget *w); diff --git a/include/sound/soc-dpcm.h b/include/sound/soc-dpcm.h index 1e7d09556fe3..ebd24753dd00 100644 --- a/include/sound/soc-dpcm.h +++ b/include/sound/soc-dpcm.h @@ -91,7 +91,6 @@ struct snd_soc_dpcm_runtime { struct list_head fe_clients; int users; - struct snd_pcm_runtime *runtime; struct snd_pcm_hw_params hw_params; /* state and update */ @@ -123,6 +122,10 @@ int snd_soc_dpcm_can_be_free_stop(struct snd_soc_pcm_runtime *fe, int snd_soc_dpcm_can_be_params(struct snd_soc_pcm_runtime *fe, struct snd_soc_pcm_runtime *be, int stream); +/* can this BE perform prepare */ +int snd_soc_dpcm_can_be_prepared(struct snd_soc_pcm_runtime *fe, + struct snd_soc_pcm_runtime *be, int stream); + /* is the current PCM operation for this FE ? */ int snd_soc_dpcm_fe_can_update(struct snd_soc_pcm_runtime *fe, int stream); diff --git a/include/sound/soc.h b/include/sound/soc.h index e58b43b5da7c..fa2337a3cf4c 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -607,6 +607,14 @@ int snd_soc_get_strobe(struct snd_kcontrol *kcontrol, int snd_soc_put_strobe(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +enum snd_soc_trigger_order { + /* start stop */ + SND_SOC_TRIGGER_ORDER_DEFAULT = 0, /* Link->Component->DAI DAI->Component->Link */ + SND_SOC_TRIGGER_ORDER_LDC, /* Link->DAI->Component Component->DAI->Link */ + + SND_SOC_TRIGGER_ORDER_MAX, +}; + /* SoC PCM stream information */ struct snd_soc_pcm_stream { const char *stream_name; @@ -633,7 +641,6 @@ struct snd_soc_compr_ops { int (*startup)(struct snd_compr_stream *); void (*shutdown)(struct snd_compr_stream *); int (*set_params)(struct snd_compr_stream *); - int (*trigger)(struct snd_compr_stream *); }; struct snd_soc_component* @@ -644,6 +651,12 @@ struct snd_soc_dai_link_component { const char *name; struct device_node *of_node; const char *dai_name; + struct of_phandle_args *dai_args; +}; + +struct snd_soc_dai_link_codec_ch_map { + unsigned int connected_cpu_id; + unsigned int ch_mask; }; struct snd_soc_dai_link { @@ -674,6 +687,7 @@ struct snd_soc_dai_link { struct snd_soc_dai_link_component *codecs; unsigned int num_codecs; + struct snd_soc_dai_link_codec_ch_map *codec_ch_maps; /* * You MAY specify the link's platform/PCM/DMA driver, either by * device name, or by DT/OF node, but not both. Some forms of link @@ -684,8 +698,11 @@ struct snd_soc_dai_link { int id; /* optional ID for machine driver link identification */ - const struct snd_soc_pcm_stream *params; - unsigned int num_params; + /* + * for Codec2Codec + */ + const struct snd_soc_pcm_stream *c2c_params; + unsigned int num_c2c_params; unsigned int dai_fmt; /* format to set on init */ @@ -705,6 +722,15 @@ struct snd_soc_dai_link { const struct snd_soc_ops *ops; const struct snd_soc_compr_ops *compr_ops; + /* + * soc_pcm_trigger() start/stop sequence. + * see also + * snd_soc_component_driver + * soc_pcm_trigger() + */ + enum snd_soc_trigger_order trigger_start; + enum snd_soc_trigger_order trigger_stop; + /* Mark this pcm with non atomic ops */ unsigned int nonatomic:1; @@ -743,12 +769,6 @@ struct snd_soc_dai_link { /* Do not create a PCM for this DAI link (Backend link) */ unsigned int ignore:1; - /* This flag will reorder stop sequence. By enabling this flag - * DMA controller stop sequence will be invoked first followed by - * CPU DAI driver stop sequence - */ - unsigned int stop_dma_first:1; - #ifdef CONFIG_SND_SOC_TOPOLOGY struct snd_soc_dobj dobj; /* For topology */ #endif @@ -875,6 +895,7 @@ asoc_link_to_platform(struct snd_soc_dai_link *link, int n) { #define COMP_DUMMY() { .name = "snd-soc-dummy", .dai_name = "snd-soc-dummy-dai", } extern struct snd_soc_dai_link_component null_dailink_component[0]; +extern struct snd_soc_dai_link_component asoc_dummy_dlc; struct snd_soc_codec_conf { @@ -1065,7 +1086,7 @@ struct snd_soc_pcm_runtime { struct snd_soc_dai_link *dai_link; struct snd_pcm_ops ops; - unsigned int params_select; /* currently selected param for dai link */ + unsigned int c2c_params_select; /* currently selected c2c_param for dai link */ /* Dynamic PCM BE runtime data */ struct snd_soc_dpcm_runtime dpcm[SNDRV_PCM_STREAM_LAST + 1]; @@ -1288,11 +1309,18 @@ unsigned int snd_soc_daifmt_parse_clock_provider_raw(struct device_node *np, snd_soc_daifmt_clock_provider_from_bitmap( \ snd_soc_daifmt_parse_clock_provider_as_bitmap(np, prefix)) +int snd_soc_get_stream_cpu(struct snd_soc_dai_link *dai_link, int stream); +int snd_soc_get_dlc(const struct of_phandle_args *args, + struct snd_soc_dai_link_component *dlc); +int snd_soc_of_get_dlc(struct device_node *of_node, + struct of_phandle_args *args, + struct snd_soc_dai_link_component *dlc, + int index); int snd_soc_get_dai_id(struct device_node *ep); int snd_soc_get_dai_name(const struct of_phandle_args *args, const char **dai_name); int snd_soc_of_get_dai_name(struct device_node *of_node, - const char **dai_name); + const char **dai_name, int index); int snd_soc_of_get_dai_link_codecs(struct device *dev, struct device_node *of_node, struct snd_soc_dai_link *dai_link); @@ -1302,11 +1330,17 @@ int snd_soc_of_get_dai_link_cpus(struct device *dev, struct snd_soc_dai_link *dai_link); void snd_soc_of_put_dai_link_cpus(struct snd_soc_dai_link *dai_link); -int snd_soc_add_pcm_runtime(struct snd_soc_card *card, - struct snd_soc_dai_link *dai_link); +int snd_soc_add_pcm_runtimes(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_link, + int num_dai_link); void snd_soc_remove_pcm_runtime(struct snd_soc_card *card, struct snd_soc_pcm_runtime *rtd); +void snd_soc_dlc_use_cpu_as_platform(struct snd_soc_dai_link_component *platforms, + struct snd_soc_dai_link_component *cpus); +struct of_phandle_args *snd_soc_copy_dai_args(struct device *dev, + struct of_phandle_args *args); +struct snd_soc_dai *snd_soc_get_dai_via_args(struct of_phandle_args *dai_args); struct snd_soc_dai *snd_soc_register_dai(struct snd_soc_component *component, struct snd_soc_dai_driver *dai_drv, bool legacy_dai_naming); @@ -1360,17 +1394,112 @@ extern struct dentry *snd_soc_debugfs_root; extern const struct dev_pm_ops snd_soc_pm_ops; -/* Helper functions */ -static inline void snd_soc_dapm_mutex_lock(struct snd_soc_dapm_context *dapm) +/* + * DAPM helper functions + */ +enum snd_soc_dapm_subclass { + SND_SOC_DAPM_CLASS_ROOT = 0, + SND_SOC_DAPM_CLASS_RUNTIME = 1, +}; + +static inline void _snd_soc_dapm_mutex_lock_root_c(struct snd_soc_card *card) +{ + mutex_lock_nested(&card->dapm_mutex, SND_SOC_DAPM_CLASS_ROOT); +} + +static inline void _snd_soc_dapm_mutex_lock_c(struct snd_soc_card *card) +{ + mutex_lock_nested(&card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); +} + +static inline void _snd_soc_dapm_mutex_unlock_c(struct snd_soc_card *card) +{ + mutex_unlock(&card->dapm_mutex); +} + +static inline void _snd_soc_dapm_mutex_assert_held_c(struct snd_soc_card *card) +{ + lockdep_assert_held(&card->dapm_mutex); +} + +static inline void _snd_soc_dapm_mutex_lock_root_d(struct snd_soc_dapm_context *dapm) +{ + _snd_soc_dapm_mutex_lock_root_c(dapm->card); +} + +static inline void _snd_soc_dapm_mutex_lock_d(struct snd_soc_dapm_context *dapm) +{ + _snd_soc_dapm_mutex_lock_c(dapm->card); +} + +static inline void _snd_soc_dapm_mutex_unlock_d(struct snd_soc_dapm_context *dapm) { - mutex_lock_nested(&dapm->card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); + _snd_soc_dapm_mutex_unlock_c(dapm->card); } -static inline void snd_soc_dapm_mutex_unlock(struct snd_soc_dapm_context *dapm) +static inline void _snd_soc_dapm_mutex_assert_held_d(struct snd_soc_dapm_context *dapm) { - mutex_unlock(&dapm->card->dapm_mutex); + _snd_soc_dapm_mutex_assert_held_c(dapm->card); } +#define snd_soc_dapm_mutex_lock_root(x) _Generic((x), \ + struct snd_soc_card * : _snd_soc_dapm_mutex_lock_root_c, \ + struct snd_soc_dapm_context * : _snd_soc_dapm_mutex_lock_root_d)(x) +#define snd_soc_dapm_mutex_lock(x) _Generic((x), \ + struct snd_soc_card * : _snd_soc_dapm_mutex_lock_c, \ + struct snd_soc_dapm_context * : _snd_soc_dapm_mutex_lock_d)(x) +#define snd_soc_dapm_mutex_unlock(x) _Generic((x), \ + struct snd_soc_card * : _snd_soc_dapm_mutex_unlock_c, \ + struct snd_soc_dapm_context * : _snd_soc_dapm_mutex_unlock_d)(x) +#define snd_soc_dapm_mutex_assert_held(x) _Generic((x), \ + struct snd_soc_card * : _snd_soc_dapm_mutex_assert_held_c, \ + struct snd_soc_dapm_context * : _snd_soc_dapm_mutex_assert_held_d)(x) + +/* + * PCM helper functions + */ +static inline void _snd_soc_dpcm_mutex_lock_c(struct snd_soc_card *card) +{ + mutex_lock_nested(&card->pcm_mutex, card->pcm_subclass); +} + +static inline void _snd_soc_dpcm_mutex_unlock_c(struct snd_soc_card *card) +{ + mutex_unlock(&card->pcm_mutex); +} + +static inline void _snd_soc_dpcm_mutex_assert_held_c(struct snd_soc_card *card) +{ + lockdep_assert_held(&card->pcm_mutex); +} + +static inline void _snd_soc_dpcm_mutex_lock_r(struct snd_soc_pcm_runtime *rtd) +{ + _snd_soc_dpcm_mutex_lock_c(rtd->card); +} + +static inline void _snd_soc_dpcm_mutex_unlock_r(struct snd_soc_pcm_runtime *rtd) +{ + _snd_soc_dpcm_mutex_unlock_c(rtd->card); +} + +static inline void _snd_soc_dpcm_mutex_assert_held_r(struct snd_soc_pcm_runtime *rtd) +{ + _snd_soc_dpcm_mutex_assert_held_c(rtd->card); +} + +#define snd_soc_dpcm_mutex_lock(x) _Generic((x), \ + struct snd_soc_card * : _snd_soc_dpcm_mutex_lock_c, \ + struct snd_soc_pcm_runtime * : _snd_soc_dpcm_mutex_lock_r)(x) + +#define snd_soc_dpcm_mutex_unlock(x) _Generic((x), \ + struct snd_soc_card * : _snd_soc_dpcm_mutex_unlock_c, \ + struct snd_soc_pcm_runtime * : _snd_soc_dpcm_mutex_unlock_r)(x) + +#define snd_soc_dpcm_mutex_assert_held(x) _Generic((x), \ + struct snd_soc_card * : _snd_soc_dpcm_mutex_assert_held_c, \ + struct snd_soc_pcm_runtime * : _snd_soc_dpcm_mutex_assert_held_r)(x) + #include <sound/soc-component.h> #include <sound/soc-card.h> #include <sound/soc-jack.h> diff --git a/include/sound/sof.h b/include/sound/sof.h index 266e66318f9c..d3c41f87ac31 100644 --- a/include/sound/sof.h +++ b/include/sound/sof.h @@ -21,6 +21,7 @@ struct snd_sof_dev; /** * enum sof_fw_state - DSP firmware state definitions * @SOF_FW_BOOT_NOT_STARTED: firmware boot is not yet started + * @SOF_DSPLESS_MODE: DSP is not used * @SOF_FW_BOOT_PREPARE: preparing for boot (firmware loading for exaqmple) * @SOF_FW_BOOT_IN_PROGRESS: firmware boot is in progress * @SOF_FW_BOOT_FAILED: firmware boot failed @@ -31,6 +32,7 @@ struct snd_sof_dev; */ enum sof_fw_state { SOF_FW_BOOT_NOT_STARTED = 0, + SOF_DSPLESS_MODE, SOF_FW_BOOT_PREPARE, SOF_FW_BOOT_IN_PROGRESS, SOF_FW_BOOT_FAILED, @@ -130,6 +132,9 @@ struct sof_dev_desc { unsigned int ipc_supported_mask; enum sof_ipc_type ipc_default; + /* The platform supports DSPless mode */ + bool dspless_mode_supported; + /* defaults paths for firmware, library and topology files */ const char *default_fw_path[SOF_IPC_TYPE_COUNT]; const char *default_lib_path[SOF_IPC_TYPE_COUNT]; diff --git a/include/sound/sof/ipc4/header.h b/include/sound/sof/ipc4/header.h index d31349bf011d..78568abe2673 100644 --- a/include/sound/sof/ipc4/header.h +++ b/include/sound/sof/ipc4/header.h @@ -176,6 +176,10 @@ enum sof_ipc4_pipeline_state { #define SOF_IPC4_GLB_PIPE_EXT_LP_MASK BIT(0) #define SOF_IPC4_GLB_PIPE_EXT_LP(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT) +#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID_SHIFT 20 +#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID_MASK GENMASK(23, 20) +#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_CORE_ID_SHIFT) + /* pipeline set state ipc msg */ #define SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT 16 #define SOF_IPC4_GLB_PIPE_STATE_ID_MASK GENMASK(23, 16) @@ -192,6 +196,35 @@ enum sof_ipc4_pipeline_state { #define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT 16 #define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID(x) ((x) << SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT) +/* chain dma ipc message */ +#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT 0 +#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK GENMASK(4, 0) +#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID(x) (((x) << SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT) & \ + SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK) + +#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT 8 +#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK GENMASK(12, 8) +#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID(x) (((x) << SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT) & \ + SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK) + +#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT 16 +#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK BIT(16) +#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT) + +#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT 17 +#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK BIT(17) +#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT) + +#define SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT 18 +#define SOF_IPC4_GLB_CHAIN_DMA_SCS_MASK BIT(18) +#define SOF_IPC4_GLB_CHAIN_DMA_SCS(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT) + +#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT 0 +#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK GENMASK(24, 0) +#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE(x) (((x) << \ + SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT) & \ + SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK) + enum sof_ipc4_channel_config { /* one channel only. */ SOF_IPC4_CHANNEL_CONFIG_MONO, diff --git a/include/sound/sof/topology.h b/include/sound/sof/topology.h index 88560281d420..906e2f327ad2 100644 --- a/include/sound/sof/topology.h +++ b/include/sound/sof/topology.h @@ -26,9 +26,9 @@ enum sof_comp_type { SOF_COMP_MIXER, SOF_COMP_MUX, SOF_COMP_SRC, - SOF_COMP_SPLITTER, + SOF_COMP_DEPRECATED0, /* Formerly SOF_COMP_SPLITTER */ SOF_COMP_TONE, - SOF_COMP_SWITCH, + SOF_COMP_DEPRECATED1, /* Formerly SOF_COMP_SWITCH */ SOF_COMP_BUFFER, SOF_COMP_EQ_IIR, SOF_COMP_EQ_FIR, diff --git a/include/sound/tas2781-dsp.h b/include/sound/tas2781-dsp.h new file mode 100644 index 000000000000..bd1b72bf47a5 --- /dev/null +++ b/include/sound/tas2781-dsp.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// +// ALSA SoC Texas Instruments TAS2781 Audio Smart Amplifier +// +// Copyright (C) 2022 - 2023 Texas Instruments Incorporated +// https://www.ti.com +// +// The TAS2781 driver implements a flexible and configurable +// algo coefficient setting for one, two, or even multiple +// TAS2781 chips. +// +// Author: Shenghao Ding <shenghao-ding@ti.com> +// Author: Kevin Lu <kevin-lu@ti.com> +// + +#ifndef __TASDEVICE_DSP_H__ +#define __TASDEVICE_DSP_H__ + +#define MAIN_ALL_DEVICES 0x0d +#define MAIN_DEVICE_A 0x01 +#define MAIN_DEVICE_B 0x08 +#define MAIN_DEVICE_C 0x10 +#define MAIN_DEVICE_D 0x14 +#define COEFF_DEVICE_A 0x03 +#define COEFF_DEVICE_B 0x0a +#define COEFF_DEVICE_C 0x11 +#define COEFF_DEVICE_D 0x15 +#define PRE_DEVICE_A 0x04 +#define PRE_DEVICE_B 0x0b +#define PRE_DEVICE_C 0x12 +#define PRE_DEVICE_D 0x16 + +#define PPC3_VERSION 0x4100 +#define PPC3_VERSION_TAS2781 0x14600 +#define TASDEVICE_DEVICE_SUM 8 +#define TASDEVICE_CONFIG_SUM 64 + +#define TASDEVICE_MAX_CHANNELS 8 + +enum tasdevice_dsp_dev_idx { + TASDEVICE_DSP_TAS_2555 = 0, + TASDEVICE_DSP_TAS_2555_STEREO, + TASDEVICE_DSP_TAS_2557_MONO, + TASDEVICE_DSP_TAS_2557_DUAL_MONO, + TASDEVICE_DSP_TAS_2559, + TASDEVICE_DSP_TAS_2563, + TASDEVICE_DSP_TAS_2563_DUAL_MONO = 7, + TASDEVICE_DSP_TAS_2563_QUAD, + TASDEVICE_DSP_TAS_2563_21, + TASDEVICE_DSP_TAS_2781, + TASDEVICE_DSP_TAS_2781_DUAL_MONO, + TASDEVICE_DSP_TAS_2781_21, + TASDEVICE_DSP_TAS_2781_QUAD, + TASDEVICE_DSP_TAS_MAX_DEVICE +}; + +struct tasdevice_fw_fixed_hdr { + unsigned int fwsize; + unsigned int ppcver; + unsigned int drv_ver; +}; + +struct tasdevice_dspfw_hdr { + struct tasdevice_fw_fixed_hdr fixed_hdr; + unsigned short device_family; + unsigned short device; + unsigned char ndev; +}; + +struct tasdev_blk { + int nr_retry; + unsigned int type; + unsigned char is_pchksum_present; + unsigned char pchksum; + unsigned char is_ychksum_present; + unsigned char ychksum; + unsigned int nr_cmds; + unsigned int blk_size; + unsigned int nr_subblocks; + unsigned char *data; +}; + +struct tasdevice_data { + char name[64]; + unsigned int nr_blk; + struct tasdev_blk *dev_blks; +}; + +struct tasdevice_prog { + unsigned int prog_size; + struct tasdevice_data dev_data; +}; + +struct tasdevice_config { + unsigned int cfg_size; + char name[64]; + struct tasdevice_data dev_data; +}; + +struct tasdevice_calibration { + struct tasdevice_data dev_data; +}; + +struct tasdevice_fw { + struct tasdevice_dspfw_hdr fw_hdr; + unsigned short nr_programs; + struct tasdevice_prog *programs; + unsigned short nr_configurations; + struct tasdevice_config *configs; + unsigned short nr_calibrations; + struct tasdevice_calibration *calibrations; + struct device *dev; +}; + +enum tasdevice_dsp_fw_state { + TASDEVICE_DSP_FW_NONE = 0, + TASDEVICE_DSP_FW_PENDING, + TASDEVICE_DSP_FW_FAIL, + TASDEVICE_DSP_FW_ALL_OK, +}; + +enum tasdevice_bin_blk_type { + TASDEVICE_BIN_BLK_COEFF = 1, + TASDEVICE_BIN_BLK_POST_POWER_UP, + TASDEVICE_BIN_BLK_PRE_SHUTDOWN, + TASDEVICE_BIN_BLK_PRE_POWER_UP, + TASDEVICE_BIN_BLK_POST_SHUTDOWN +}; + +struct tasdevice_rca_hdr { + unsigned int img_sz; + unsigned int checksum; + unsigned int binary_version_num; + unsigned int drv_fw_version; + unsigned char plat_type; + unsigned char dev_family; + unsigned char reserve; + unsigned char ndev; + unsigned char devs[TASDEVICE_DEVICE_SUM]; + unsigned int nconfig; + unsigned int config_size[TASDEVICE_CONFIG_SUM]; +}; + +struct tasdev_blk_data { + unsigned char dev_idx; + unsigned char block_type; + unsigned short yram_checksum; + unsigned int block_size; + unsigned int n_subblks; + unsigned char *regdata; +}; + +struct tasdevice_config_info { + unsigned int nblocks; + unsigned int real_nblocks; + unsigned char active_dev; + struct tasdev_blk_data **blk_data; +}; + +struct tasdevice_rca { + struct tasdevice_rca_hdr fw_hdr; + int ncfgs; + struct tasdevice_config_info **cfg_info; + int profile_cfg_id; +}; + +void tasdevice_select_cfg_blk(void *context, int conf_no, + unsigned char block_type); +void tasdevice_config_info_remove(void *context); +void tasdevice_dsp_remove(void *context); +int tasdevice_dsp_parser(void *context); +int tasdevice_rca_parser(void *context, const struct firmware *fmw); +void tasdevice_dsp_remove(void *context); +void tasdevice_calbin_remove(void *context); +int tasdevice_select_tuningprm_cfg(void *context, int prm, + int cfg_no, int rca_conf_no); +int tasdevice_prmg_load(void *context, int prm_no); +int tasdevice_prmg_calibdata_load(void *context, int prm_no); +void tasdevice_tuning_switch(void *context, int state); +int tas2781_load_calibration(void *context, char *file_name, + unsigned short i); + +#endif diff --git a/include/sound/tas2781-tlv.h b/include/sound/tas2781-tlv.h new file mode 100644 index 000000000000..4038dd421150 --- /dev/null +++ b/include/sound/tas2781-tlv.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// +// ALSA SoC Texas Instruments TAS2781 Audio Smart Amplifier +// +// Copyright (C) 2022 - 2023 Texas Instruments Incorporated +// https://www.ti.com +// +// The TAS2781 driver implements a flexible and configurable +// algo coefficient setting for one, two, or even multiple +// TAS2781 chips. +// +// Author: Shenghao Ding <shenghao-ding@ti.com> +// + +#ifndef __TAS2781_TLV_H__ +#define __TAS2781_TLV_H__ + +static const DECLARE_TLV_DB_SCALE(dvc_tlv, -10000, 100, 0); +static const DECLARE_TLV_DB_SCALE(amp_vol_tlv, 1100, 50, 0); + +#endif diff --git a/include/sound/tas2781.h b/include/sound/tas2781.h new file mode 100644 index 000000000000..a6c808b22318 --- /dev/null +++ b/include/sound/tas2781.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// +// ALSA SoC Texas Instruments TAS2781 Audio Smart Amplifier +// +// Copyright (C) 2022 - 2023 Texas Instruments Incorporated +// https://www.ti.com +// +// The TAS2781 driver implements a flexible and configurable +// algo coefficient setting for one, two, or even multiple +// TAS2781 chips. +// +// Author: Shenghao Ding <shenghao-ding@ti.com> +// Author: Kevin Lu <kevin-lu@ti.com> +// + +#ifndef __TAS2781_H__ +#define __TAS2781_H__ + +#include "tas2781-dsp.h" + +/* version number */ +#define TAS2781_DRV_VER 1 +#define SMARTAMP_MODULE_NAME "tas2781" +#define TAS2781_GLOBAL_ADDR 0x40 +#define TASDEVICE_RATES (SNDRV_PCM_RATE_44100 |\ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |\ + SNDRV_PCM_RATE_88200) + +#define TASDEVICE_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) + +/*PAGE Control Register (available in page0 of each book) */ +#define TASDEVICE_PAGE_SELECT 0x00 +#define TASDEVICE_BOOKCTL_PAGE 0x00 +#define TASDEVICE_BOOKCTL_REG 127 +#define TASDEVICE_BOOK_ID(reg) (reg / (256 * 128)) +#define TASDEVICE_PAGE_ID(reg) ((reg % (256 * 128)) / 128) +#define TASDEVICE_PAGE_REG(reg) ((reg % (256 * 128)) % 128) +#define TASDEVICE_PGRG(reg) (reg % (256 * 128)) +#define TASDEVICE_REG(book, page, reg) (((book * 256 * 128) + \ + (page * 128)) + reg) + +/*Software Reset */ +#define TAS2781_REG_SWRESET TASDEVICE_REG(0x0, 0X0, 0x01) +#define TAS2781_REG_SWRESET_RESET BIT(0) + +/*I2C Checksum */ +#define TASDEVICE_I2CChecksum TASDEVICE_REG(0x0, 0x0, 0x7E) + +/* Volume control */ +#define TAS2781_DVC_LVL TASDEVICE_REG(0x0, 0x0, 0x1A) +#define TAS2781_AMP_LEVEL TASDEVICE_REG(0x0, 0x0, 0x03) +#define TAS2781_AMP_LEVEL_MASK GENMASK(5, 1) + +#define TASDEVICE_CMD_SING_W 0x1 +#define TASDEVICE_CMD_BURST 0x2 +#define TASDEVICE_CMD_DELAY 0x3 +#define TASDEVICE_CMD_FIELD_W 0x4 + +enum audio_device { + TAS2781 = 0, +}; + +enum device_catlog_id { + LENOVO = 0, + OTHERS +}; + +struct tasdevice { + struct tasdevice_fw *cali_data_fmw; + unsigned int dev_addr; + unsigned int err_code; + unsigned char cur_book; + short cur_prog; + short cur_conf; + bool is_loading; + bool is_loaderr; +}; + +struct tasdevice_irqinfo { + int irq_gpio; + int irq; +}; + +struct calidata { + unsigned char *data; + unsigned long total_sz; +}; + +struct tasdevice_priv { + struct tasdevice tasdevice[TASDEVICE_MAX_CHANNELS]; + struct tasdevice_irqinfo irq_info; + struct tasdevice_rca rcabin; + struct calidata cali_data; + struct tasdevice_fw *fmw; + struct gpio_desc *reset; + struct mutex codec_lock; + struct regmap *regmap; + struct device *dev; + struct tm tm; + + enum device_catlog_id catlog_id; + const char *acpi_subsystem_id; + unsigned char cal_binaryname[TASDEVICE_MAX_CHANNELS][64]; + unsigned char crc8_lkp_tbl[CRC8_TABLE_SIZE]; + unsigned char coef_binaryname[64]; + unsigned char rca_binaryname[64]; + unsigned char dev_name[32]; + unsigned char ndev; + unsigned int magic_num; + unsigned int chip_id; + unsigned int sysclk; + + int cur_prog; + int cur_conf; + int fw_state; + int index; + void *client; + void *codec; + bool force_fwload_status; + bool playback_started; + bool isacpi; + int (*fw_parse_variable_header)(struct tasdevice_priv *tas_priv, + const struct firmware *fmw, int offset); + int (*fw_parse_program_data)(struct tasdevice_priv *tas_priv, + struct tasdevice_fw *tas_fmw, + const struct firmware *fmw, int offset); + int (*fw_parse_configuration_data)(struct tasdevice_priv *tas_priv, + struct tasdevice_fw *tas_fmw, + const struct firmware *fmw, int offset); + int (*tasdevice_load_block)(struct tasdevice_priv *tas_priv, + struct tasdev_blk *block); +}; + +void tas2781_reset(struct tasdevice_priv *tas_dev); +int tascodec_init(struct tasdevice_priv *tas_priv, void *codec, + void (*cont)(const struct firmware *fw, void *context)); +struct tasdevice_priv *tasdevice_kzalloc(struct i2c_client *i2c); +int tasdevice_init(struct tasdevice_priv *tas_priv); +void tasdevice_remove(struct tasdevice_priv *tas_priv); +int tasdevice_dev_read(struct tasdevice_priv *tas_priv, + unsigned short chn, unsigned int reg, unsigned int *value); +int tasdevice_dev_write(struct tasdevice_priv *tas_priv, + unsigned short chn, unsigned int reg, unsigned int value); +int tasdevice_dev_bulk_write( + struct tasdevice_priv *tas_priv, unsigned short chn, + unsigned int reg, unsigned char *p_data, unsigned int n_length); +int tasdevice_dev_bulk_read(struct tasdevice_priv *tas_priv, + unsigned short chn, unsigned int reg, unsigned char *p_data, + unsigned int n_length); +int tasdevice_dev_update_bits( + struct tasdevice_priv *tasdevice, unsigned short chn, + unsigned int reg, unsigned int mask, unsigned int value); +int tasdevice_amp_putvol(struct tasdevice_priv *tas_priv, + struct snd_ctl_elem_value *ucontrol, struct soc_mixer_control *mc); +int tasdevice_amp_getvol(struct tasdevice_priv *tas_priv, + struct snd_ctl_elem_value *ucontrol, struct soc_mixer_control *mc); +int tasdevice_digital_putvol(struct tasdevice_priv *tas_priv, + struct snd_ctl_elem_value *ucontrol, struct soc_mixer_control *mc); +int tasdevice_digital_getvol(struct tasdevice_priv *tas_priv, + struct snd_ctl_elem_value *ucontrol, struct soc_mixer_control *mc); + +#endif /* __TAS2781_H__ */ diff --git a/include/sound/uda134x.h b/include/sound/uda134x.h deleted file mode 100644 index db82516da162..000000000000 --- a/include/sound/uda134x.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * uda134x.h -- UDA134x ALSA SoC Codec driver - * - * Copyright 2007 Dension Audio Systems Ltd. - * Author: Zoltan Devai - */ - -#ifndef _UDA134X_H -#define _UDA134X_H - -#include <sound/l3.h> - -struct uda134x_platform_data { - struct l3_pins l3; - void (*power) (int); - int model; -#define UDA134X_UDA1340 1 -#define UDA134X_UDA1341 2 -#define UDA134X_UDA1344 3 -#define UDA134X_UDA1345 4 -}; - -#endif /* _UDA134X_H */ diff --git a/include/sound/ump.h b/include/sound/ump.h new file mode 100644 index 000000000000..91238dabe307 --- /dev/null +++ b/include/sound/ump.h @@ -0,0 +1,269 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Universal MIDI Packet (UMP) Support + */ +#ifndef __SOUND_UMP_H +#define __SOUND_UMP_H + +#include <sound/rawmidi.h> + +struct snd_ump_endpoint; +struct snd_ump_block; +struct snd_ump_ops; +struct ump_cvt_to_ump; +struct snd_seq_ump_ops; + +struct snd_ump_endpoint { + struct snd_rawmidi core; /* raw UMP access */ + + struct snd_ump_endpoint_info info; + + const struct snd_ump_ops *ops; /* UMP ops set by the driver */ + struct snd_rawmidi_substream *substreams[2]; /* opened substreams */ + + void *private_data; + void (*private_free)(struct snd_ump_endpoint *ump); + + /* UMP Stream message processing */ + u32 stream_wait_for; /* expected stream message status */ + bool stream_finished; /* set when message has been processed */ + bool parsed; /* UMP / FB parse finished? */ + bool no_process_stream; /* suppress UMP stream messages handling */ + wait_queue_head_t stream_wait; + struct snd_rawmidi_file stream_rfile; + + struct list_head block_list; /* list of snd_ump_block objects */ + + /* intermediate buffer for UMP input */ + u32 input_buf[4]; + int input_buf_head; + int input_pending; + + struct mutex open_mutex; + +#if IS_ENABLED(CONFIG_SND_UMP_LEGACY_RAWMIDI) + spinlock_t legacy_locks[2]; + struct snd_rawmidi *legacy_rmidi; + struct snd_rawmidi_substream *legacy_substreams[2][SNDRV_UMP_MAX_GROUPS]; + unsigned char legacy_mapping[SNDRV_UMP_MAX_GROUPS]; + + /* for legacy output; need to open the actual substream unlike input */ + int legacy_out_opens; + struct snd_rawmidi_file legacy_out_rfile; + struct ump_cvt_to_ump *out_cvts; +#endif + +#if IS_ENABLED(CONFIG_SND_SEQUENCER) + struct snd_seq_device *seq_dev; + const struct snd_seq_ump_ops *seq_ops; + void *seq_client; +#endif +}; + +/* ops filled by UMP drivers */ +struct snd_ump_ops { + int (*open)(struct snd_ump_endpoint *ump, int dir); + void (*close)(struct snd_ump_endpoint *ump, int dir); + void (*trigger)(struct snd_ump_endpoint *ump, int dir, int up); + void (*drain)(struct snd_ump_endpoint *ump, int dir); +}; + +/* ops filled by sequencer binding */ +struct snd_seq_ump_ops { + void (*input_receive)(struct snd_ump_endpoint *ump, + const u32 *data, int words); + int (*notify_fb_change)(struct snd_ump_endpoint *ump, + struct snd_ump_block *fb); + int (*switch_protocol)(struct snd_ump_endpoint *ump); +}; + +struct snd_ump_block { + struct snd_ump_block_info info; + struct snd_ump_endpoint *ump; + + void *private_data; + void (*private_free)(struct snd_ump_block *blk); + + struct list_head list; +}; + +#define rawmidi_to_ump(rmidi) container_of(rmidi, struct snd_ump_endpoint, core) + +int snd_ump_endpoint_new(struct snd_card *card, char *id, int device, + int output, int input, + struct snd_ump_endpoint **ump_ret); +int snd_ump_parse_endpoint(struct snd_ump_endpoint *ump); +int snd_ump_block_new(struct snd_ump_endpoint *ump, unsigned int blk, + unsigned int direction, unsigned int first_group, + unsigned int num_groups, struct snd_ump_block **blk_ret); +int snd_ump_receive(struct snd_ump_endpoint *ump, const u32 *buffer, int count); +int snd_ump_transmit(struct snd_ump_endpoint *ump, u32 *buffer, int count); + +#if IS_ENABLED(CONFIG_SND_UMP_LEGACY_RAWMIDI) +int snd_ump_attach_legacy_rawmidi(struct snd_ump_endpoint *ump, + char *id, int device); +#else +static inline int snd_ump_attach_legacy_rawmidi(struct snd_ump_endpoint *ump, + char *id, int device) +{ + return 0; +} +#endif + +int snd_ump_receive_ump_val(struct snd_ump_endpoint *ump, u32 val); +int snd_ump_switch_protocol(struct snd_ump_endpoint *ump, unsigned int protocol); + +/* + * Some definitions for UMP + */ + +/* MIDI 2.0 Message Type */ +enum { + UMP_MSG_TYPE_UTILITY = 0x00, + UMP_MSG_TYPE_SYSTEM = 0x01, + UMP_MSG_TYPE_MIDI1_CHANNEL_VOICE = 0x02, + UMP_MSG_TYPE_DATA = 0x03, + UMP_MSG_TYPE_MIDI2_CHANNEL_VOICE = 0x04, + UMP_MSG_TYPE_EXTENDED_DATA = 0x05, + UMP_MSG_TYPE_FLEX_DATA = 0x0d, + UMP_MSG_TYPE_STREAM = 0x0f, +}; + +/* MIDI 2.0 SysEx / Data Status; same values for both 7-bit and 8-bit SysEx */ +enum { + UMP_SYSEX_STATUS_SINGLE = 0, + UMP_SYSEX_STATUS_START = 1, + UMP_SYSEX_STATUS_CONTINUE = 2, + UMP_SYSEX_STATUS_END = 3, +}; + +/* UMP Utility Type Status (type 0x0) */ +enum { + UMP_UTILITY_MSG_STATUS_NOOP = 0x00, + UMP_UTILITY_MSG_STATUS_JR_CLOCK = 0x01, + UMP_UTILITY_MSG_STATUS_JR_TSTAMP = 0x02, + UMP_UTILITY_MSG_STATUS_DCTPQ = 0x03, + UMP_UTILITY_MSG_STATUS_DC = 0x04, +}; + +/* UMP Stream Message Status (type 0xf) */ +enum { + UMP_STREAM_MSG_STATUS_EP_DISCOVERY = 0x00, + UMP_STREAM_MSG_STATUS_EP_INFO = 0x01, + UMP_STREAM_MSG_STATUS_DEVICE_INFO = 0x02, + UMP_STREAM_MSG_STATUS_EP_NAME = 0x03, + UMP_STREAM_MSG_STATUS_PRODUCT_ID = 0x04, + UMP_STREAM_MSG_STATUS_STREAM_CFG_REQUEST = 0x05, + UMP_STREAM_MSG_STATUS_STREAM_CFG = 0x06, + UMP_STREAM_MSG_STATUS_FB_DISCOVERY = 0x10, + UMP_STREAM_MSG_STATUS_FB_INFO = 0x11, + UMP_STREAM_MSG_STATUS_FB_NAME = 0x12, + UMP_STREAM_MSG_STATUS_START_CLIP = 0x20, + UMP_STREAM_MSG_STATUS_END_CLIP = 0x21, +}; + +/* UMP Endpoint Discovery filter bitmap */ +enum { + UMP_STREAM_MSG_REQUEST_EP_INFO = (1U << 0), + UMP_STREAM_MSG_REQUEST_DEVICE_INFO = (1U << 1), + UMP_STREAM_MSG_REQUEST_EP_NAME = (1U << 2), + UMP_STREAM_MSG_REQUEST_PRODUCT_ID = (1U << 3), + UMP_STREAM_MSG_REQUEST_STREAM_CFG = (1U << 4), +}; + +/* UMP Function Block Discovery filter bitmap */ +enum { + UMP_STREAM_MSG_REQUEST_FB_INFO = (1U << 0), + UMP_STREAM_MSG_REQUEST_FB_NAME = (1U << 1), +}; + +/* UMP Endpoint Info capability bits (used for protocol request/notify, too) */ +enum { + UMP_STREAM_MSG_EP_INFO_CAP_TXJR = (1U << 0), /* Sending JRTS */ + UMP_STREAM_MSG_EP_INFO_CAP_RXJR = (1U << 1), /* Receiving JRTS */ + UMP_STREAM_MSG_EP_INFO_CAP_MIDI1 = (1U << 8), /* MIDI 1.0 */ + UMP_STREAM_MSG_EP_INFO_CAP_MIDI2 = (1U << 9), /* MIDI 2.0 */ +}; + +/* UMP EP / FB name string format; same as SysEx string handling */ +enum { + UMP_STREAM_MSG_FORMAT_SINGLE = 0, + UMP_STREAM_MSG_FORMAT_START = 1, + UMP_STREAM_MSG_FORMAT_CONTINUE = 2, + UMP_STREAM_MSG_FORMAT_END = 3, +}; + +/* + * Helpers for retrieving / filling bits from UMP + */ +/* get the message type (4bit) from a UMP packet (header) */ +static inline unsigned char ump_message_type(u32 data) +{ + return data >> 28; +} + +/* get the group number (0-based, 4bit) from a UMP packet (header) */ +static inline unsigned char ump_message_group(u32 data) +{ + return (data >> 24) & 0x0f; +} + +/* get the MIDI status code (4bit) from a UMP packet (header) */ +static inline unsigned char ump_message_status_code(u32 data) +{ + return (data >> 20) & 0x0f; +} + +/* get the MIDI channel number (0-based, 4bit) from a UMP packet (header) */ +static inline unsigned char ump_message_channel(u32 data) +{ + return (data >> 16) & 0x0f; +} + +/* get the MIDI status + channel combo byte (8bit) from a UMP packet (header) */ +static inline unsigned char ump_message_status_channel(u32 data) +{ + return (data >> 16) & 0xff; +} + +/* compose a UMP packet (header) from type, group and status values */ +static inline u32 ump_compose(unsigned char type, unsigned char group, + unsigned char status, unsigned char channel) +{ + return ((u32)type << 28) | ((u32)group << 24) | ((u32)status << 20) | + ((u32)channel << 16); +} + +/* get SysEx message status (for both 7 and 8bits) from a UMP packet (header) */ +static inline unsigned char ump_sysex_message_status(u32 data) +{ + return (data >> 20) & 0xf; +} + +/* get SysEx message length (for both 7 and 8bits) from a UMP packet (header) */ +static inline unsigned char ump_sysex_message_length(u32 data) +{ + return (data >> 16) & 0xf; +} + +/* For Stream Messages */ +static inline unsigned char ump_stream_message_format(u32 data) +{ + return (data >> 26) & 0x03; +} + +static inline unsigned int ump_stream_message_status(u32 data) +{ + return (data >> 16) & 0x3ff; +} + +static inline u32 ump_stream_compose(unsigned char status, unsigned short form) +{ + return (UMP_MSG_TYPE_STREAM << 28) | ((u32)form << 26) | + ((u32)status << 16); +} + +#define ump_is_groupless_msg(type) \ + ((type) == UMP_MSG_TYPE_UTILITY || (type) == UMP_MSG_TYPE_STREAM) + +#endif /* __SOUND_UMP_H */ diff --git a/include/sound/ump_convert.h b/include/sound/ump_convert.h new file mode 100644 index 000000000000..28c364c63245 --- /dev/null +++ b/include/sound/ump_convert.h @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#ifndef __SOUND_UMP_CONVERT_H +#define __SOUND_UMP_CONVERT_H + +#include <sound/ump_msg.h> + +/* context for converting from legacy control messages to UMP packet */ +struct ump_cvt_to_ump_bank { + bool rpn_set; + bool nrpn_set; + bool bank_set; + unsigned char cc_rpn_msb, cc_rpn_lsb; + unsigned char cc_nrpn_msb, cc_nrpn_lsb; + unsigned char cc_data_msb, cc_data_lsb; + unsigned char cc_bank_msb, cc_bank_lsb; +}; + +/* context for converting from MIDI1 byte stream to UMP packet */ +struct ump_cvt_to_ump { + /* MIDI1 intermediate buffer */ + unsigned char buf[4]; + int len; + int cmd_bytes; + + /* UMP output packet */ + u32 ump[4]; + int ump_bytes; + + /* various status */ + unsigned int in_sysex; + struct ump_cvt_to_ump_bank bank[16]; /* per channel */ +}; + +int snd_ump_convert_from_ump(const u32 *data, unsigned char *dst, + unsigned char *group_ret); +void snd_ump_convert_to_ump(struct ump_cvt_to_ump *cvt, unsigned char group, + unsigned int protocol, unsigned char c); + +/* reset the converter context, called at each open to ump */ +static inline void snd_ump_convert_reset(struct ump_cvt_to_ump *ctx) +{ + memset(ctx, 0, sizeof(*ctx)); + +} + +#endif /* __SOUND_UMP_CONVERT_H */ diff --git a/include/sound/ump_msg.h b/include/sound/ump_msg.h new file mode 100644 index 000000000000..72f60ddfea75 --- /dev/null +++ b/include/sound/ump_msg.h @@ -0,0 +1,765 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Universal MIDI Packet (UMP): Message Definitions + */ +#ifndef __SOUND_UMP_MSG_H +#define __SOUND_UMP_MSG_H + +/* MIDI 1.0 / 2.0 Status Code (4bit) */ +enum { + UMP_MSG_STATUS_PER_NOTE_RCC = 0x0, + UMP_MSG_STATUS_PER_NOTE_ACC = 0x1, + UMP_MSG_STATUS_RPN = 0x2, + UMP_MSG_STATUS_NRPN = 0x3, + UMP_MSG_STATUS_RELATIVE_RPN = 0x4, + UMP_MSG_STATUS_RELATIVE_NRPN = 0x5, + UMP_MSG_STATUS_PER_NOTE_PITCH_BEND = 0x6, + UMP_MSG_STATUS_NOTE_OFF = 0x8, + UMP_MSG_STATUS_NOTE_ON = 0x9, + UMP_MSG_STATUS_POLY_PRESSURE = 0xa, + UMP_MSG_STATUS_CC = 0xb, + UMP_MSG_STATUS_PROGRAM = 0xc, + UMP_MSG_STATUS_CHANNEL_PRESSURE = 0xd, + UMP_MSG_STATUS_PITCH_BEND = 0xe, + UMP_MSG_STATUS_PER_NOTE_MGMT = 0xf, +}; + +/* MIDI 1.0 Channel Control (7bit) */ +enum { + UMP_CC_BANK_SELECT = 0, + UMP_CC_MODULATION = 1, + UMP_CC_BREATH = 2, + UMP_CC_FOOT = 4, + UMP_CC_PORTAMENTO_TIME = 5, + UMP_CC_DATA = 6, + UMP_CC_VOLUME = 7, + UMP_CC_BALANCE = 8, + UMP_CC_PAN = 10, + UMP_CC_EXPRESSION = 11, + UMP_CC_EFFECT_CONTROL_1 = 12, + UMP_CC_EFFECT_CONTROL_2 = 13, + UMP_CC_GP_1 = 16, + UMP_CC_GP_2 = 17, + UMP_CC_GP_3 = 18, + UMP_CC_GP_4 = 19, + UMP_CC_BANK_SELECT_LSB = 32, + UMP_CC_MODULATION_LSB = 33, + UMP_CC_BREATH_LSB = 34, + UMP_CC_FOOT_LSB = 36, + UMP_CC_PORTAMENTO_TIME_LSB = 37, + UMP_CC_DATA_LSB = 38, + UMP_CC_VOLUME_LSB = 39, + UMP_CC_BALANCE_LSB = 40, + UMP_CC_PAN_LSB = 42, + UMP_CC_EXPRESSION_LSB = 43, + UMP_CC_EFFECT1_LSB = 44, + UMP_CC_EFFECT2_LSB = 45, + UMP_CC_GP_1_LSB = 48, + UMP_CC_GP_2_LSB = 49, + UMP_CC_GP_3_LSB = 50, + UMP_CC_GP_4_LSB = 51, + UMP_CC_SUSTAIN = 64, + UMP_CC_PORTAMENTO_SWITCH = 65, + UMP_CC_SOSTENUTO = 66, + UMP_CC_SOFT_PEDAL = 67, + UMP_CC_LEGATO = 68, + UMP_CC_HOLD_2 = 69, + UMP_CC_SOUND_CONTROLLER_1 = 70, + UMP_CC_SOUND_CONTROLLER_2 = 71, + UMP_CC_SOUND_CONTROLLER_3 = 72, + UMP_CC_SOUND_CONTROLLER_4 = 73, + UMP_CC_SOUND_CONTROLLER_5 = 74, + UMP_CC_SOUND_CONTROLLER_6 = 75, + UMP_CC_SOUND_CONTROLLER_7 = 76, + UMP_CC_SOUND_CONTROLLER_8 = 77, + UMP_CC_SOUND_CONTROLLER_9 = 78, + UMP_CC_SOUND_CONTROLLER_10 = 79, + UMP_CC_GP_5 = 80, + UMP_CC_GP_6 = 81, + UMP_CC_GP_7 = 82, + UMP_CC_GP_8 = 83, + UMP_CC_PORTAMENTO_CONTROL = 84, + UMP_CC_EFFECT_1 = 91, + UMP_CC_EFFECT_2 = 92, + UMP_CC_EFFECT_3 = 93, + UMP_CC_EFFECT_4 = 94, + UMP_CC_EFFECT_5 = 95, + UMP_CC_DATA_INC = 96, + UMP_CC_DATA_DEC = 97, + UMP_CC_NRPN_LSB = 98, + UMP_CC_NRPN_MSB = 99, + UMP_CC_RPN_LSB = 100, + UMP_CC_RPN_MSB = 101, + UMP_CC_ALL_SOUND_OFF = 120, + UMP_CC_RESET_ALL = 121, + UMP_CC_LOCAL_CONTROL = 122, + UMP_CC_ALL_NOTES_OFF = 123, + UMP_CC_OMNI_OFF = 124, + UMP_CC_OMNI_ON = 125, + UMP_CC_POLY_OFF = 126, + UMP_CC_POLY_ON = 127, +}; + +/* MIDI 1.0 / 2.0 System Messages (0xfx) */ +enum { + UMP_SYSTEM_STATUS_MIDI_TIME_CODE = 0xf1, + UMP_SYSTEM_STATUS_SONG_POSITION = 0xf2, + UMP_SYSTEM_STATUS_SONG_SELECT = 0xf3, + UMP_SYSTEM_STATUS_TUNE_REQUEST = 0xf6, + UMP_SYSTEM_STATUS_TIMING_CLOCK = 0xf8, + UMP_SYSTEM_STATUS_START = 0xfa, + UMP_SYSTEM_STATUS_CONTINUE = 0xfb, + UMP_SYSTEM_STATUS_STOP = 0xfc, + UMP_SYSTEM_STATUS_ACTIVE_SENSING = 0xfe, + UMP_SYSTEM_STATUS_RESET = 0xff, +}; + +/* MIDI 1.0 Realtime and SysEx status messages (0xfx) */ +enum { + UMP_MIDI1_MSG_REALTIME = 0xf0, /* mask */ + UMP_MIDI1_MSG_SYSEX_START = 0xf0, + UMP_MIDI1_MSG_SYSEX_END = 0xf7, +}; + +/* + * UMP Message Definitions + */ + +/* MIDI 1.0 Note Off / Note On (32bit) */ +struct snd_ump_midi1_msg_note { +#ifdef __BIG_ENDIAN_BITFIELD + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 note:8; + u32 velocity:8; +#else + u32 velocity:8; + u32 note:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; +#endif +} __packed; + +/* MIDI 1.0 Poly Pressure (32bit) */ +struct snd_ump_midi1_msg_paf { +#ifdef __BIG_ENDIAN_BITFIELD + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 note:8; + u32 data:8; +#else + u32 data:8; + u32 note:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; +#endif +} __packed; + +/* MIDI 1.0 Control Change (32bit) */ +struct snd_ump_midi1_msg_cc { +#ifdef __BIG_ENDIAN_BITFIELD + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 index:8; + u32 data:8; +#else + u32 data:8; + u32 index:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; +#endif +} __packed; + +/* MIDI 1.0 Program Change (32bit) */ +struct snd_ump_midi1_msg_program { +#ifdef __BIG_ENDIAN_BITFIELD + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 program:8; + u32 reserved:8; +#else + u32 reserved:8; + u32 program:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; +#endif +} __packed; + +/* MIDI 1.0 Channel Pressure (32bit) */ +struct snd_ump_midi1_msg_caf { +#ifdef __BIG_ENDIAN_BITFIELD + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 data:8; + u32 reserved:8; +#else + u32 reserved:8; + u32 data:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; +#endif +} __packed; + +/* MIDI 1.0 Pitch Bend (32bit) */ +struct snd_ump_midi1_msg_pitchbend { +#ifdef __BIG_ENDIAN_BITFIELD + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 data_lsb:8; + u32 data_msb:8; +#else + u32 data_msb:8; + u32 data_lsb:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; +#endif +} __packed; + +/* System Common and Real Time messages (32bit); no channel field */ +struct snd_ump_system_msg { +#ifdef __BIG_ENDIAN_BITFIELD + u32 type:4; + u32 group:4; + u32 status:8; + u32 parm1:8; + u32 parm2:8; +#else + u32 parm2:8; + u32 parm1:8; + u32 status:8; + u32 group:4; + u32 type:4; +#endif +} __packed; + +/* MIDI 1.0 UMP CVM (32bit) */ +union snd_ump_midi1_msg { + struct snd_ump_midi1_msg_note note; + struct snd_ump_midi1_msg_paf paf; + struct snd_ump_midi1_msg_cc cc; + struct snd_ump_midi1_msg_program pg; + struct snd_ump_midi1_msg_caf caf; + struct snd_ump_midi1_msg_pitchbend pb; + struct snd_ump_system_msg system; + u32 raw; +}; + +/* MIDI 2.0 Note Off / Note On (64bit) */ +struct snd_ump_midi2_msg_note { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 note:8; + u32 attribute_type:8; + /* 1 */ + u32 velocity:16; + u32 attribute_data:16; +#else + /* 0 */ + u32 attribute_type:8; + u32 note:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 attribute_data:16; + u32 velocity:16; +#endif +} __packed; + +/* MIDI 2.0 Poly Pressure (64bit) */ +struct snd_ump_midi2_msg_paf { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 note:8; + u32 reserved:8; + /* 1 */ + u32 data; +#else + /* 0 */ + u32 reserved:8; + u32 note:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 data; +#endif +} __packed; + +/* MIDI 2.0 Per-Note Controller (64bit) */ +struct snd_ump_midi2_msg_pernote_cc { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 note:8; + u32 index:8; + /* 1 */ + u32 data; +#else + /* 0 */ + u32 index:8; + u32 note:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 data; +#endif +} __packed; + +/* MIDI 2.0 Per-Note Management (64bit) */ +struct snd_ump_midi2_msg_pernote_mgmt { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 note:8; + u32 flags:8; + /* 1 */ + u32 reserved; +#else + /* 0 */ + u32 flags:8; + u32 note:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 reserved; +#endif +} __packed; + +/* MIDI 2.0 Control Change (64bit) */ +struct snd_ump_midi2_msg_cc { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 index:8; + u32 reserved:8; + /* 1 */ + u32 data; +#else + /* 0 */ + u32 reserved:8; + u32 index:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 data; +#endif +} __packed; + +/* MIDI 2.0 Registered Controller (RPN) / Assignable Controller (NRPN) (64bit) */ +struct snd_ump_midi2_msg_rpn { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 bank:8; + u32 index:8; + /* 1 */ + u32 data; +#else + /* 0 */ + u32 index:8; + u32 bank:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 data; +#endif +} __packed; + +/* MIDI 2.0 Program Change (64bit) */ +struct snd_ump_midi2_msg_program { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 reserved:15; + u32 bank_valid:1; + /* 1 */ + u32 program:8; + u32 reserved2:8; + u32 bank_msb:8; + u32 bank_lsb:8; +#else + /* 0 */ + u32 bank_valid:1; + u32 reserved:15; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 bank_lsb:8; + u32 bank_msb:8; + u32 reserved2:8; + u32 program:8; +#endif +} __packed; + +/* MIDI 2.0 Channel Pressure (64bit) */ +struct snd_ump_midi2_msg_caf { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 reserved:16; + /* 1 */ + u32 data; +#else + /* 0 */ + u32 reserved:16; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 data; +#endif +} __packed; + +/* MIDI 2.0 Pitch Bend (64bit) */ +struct snd_ump_midi2_msg_pitchbend { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 reserved:16; + /* 1 */ + u32 data; +#else + /* 0 */ + u32 reserved:16; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 data; +#endif +} __packed; + +/* MIDI 2.0 Per-Note Pitch Bend (64bit) */ +struct snd_ump_midi2_msg_pernote_pitchbend { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 note:8; + u32 reserved:8; + /* 1 */ + u32 data; +#else + /* 0 */ + u32 reserved:8; + u32 note:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 data; +#endif +} __packed; + +/* MIDI 2.0 UMP CVM (64bit) */ +union snd_ump_midi2_msg { + struct snd_ump_midi2_msg_note note; + struct snd_ump_midi2_msg_paf paf; + struct snd_ump_midi2_msg_pernote_cc pernote_cc; + struct snd_ump_midi2_msg_pernote_mgmt pernote_mgmt; + struct snd_ump_midi2_msg_cc cc; + struct snd_ump_midi2_msg_rpn rpn; + struct snd_ump_midi2_msg_program pg; + struct snd_ump_midi2_msg_caf caf; + struct snd_ump_midi2_msg_pitchbend pb; + struct snd_ump_midi2_msg_pernote_pitchbend pernote_pb; + u32 raw[2]; +}; + +/* UMP Stream Message: Endpoint Discovery (128bit) */ +struct snd_ump_stream_msg_ep_discovery { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 format:2; + u32 status:10; + u32 ump_version_major:8; + u32 ump_version_minor:8; + /* 1 */ + u32 reserved:24; + u32 filter_bitmap:8; + /* 2-3 */ + u32 reserved2[2]; +#else + /* 0 */ + u32 ump_version_minor:8; + u32 ump_version_major:8; + u32 status:10; + u32 format:2; + u32 type:4; + /* 1 */ + u32 filter_bitmap:8; + u32 reserved:24; + /* 2-3 */ + u32 reserved2[2]; +#endif +} __packed; + +/* UMP Stream Message: Endpoint Info Notification (128bit) */ +struct snd_ump_stream_msg_ep_info { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 format:2; + u32 status:10; + u32 ump_version_major:8; + u32 ump_version_minor:8; + /* 1 */ + u32 static_function_block:1; + u32 num_function_blocks:7; + u32 reserved:8; + u32 protocol:8; + u32 reserved2:6; + u32 jrts:2; + /* 2-3 */ + u32 reserved3[2]; +#else + /* 0 */ + u32 ump_version_minor:8; + u32 ump_version_major:8; + u32 status:10; + u32 format:2; + u32 type:4; + /* 1 */ + u32 jrts:2; + u32 reserved2:6; + u32 protocol:8; + u32 reserved:8; + u32 num_function_blocks:7; + u32 static_function_block:1; + /* 2-3 */ + u32 reserved3[2]; +#endif +} __packed; + +/* UMP Stream Message: Device Info Notification (128bit) */ +struct snd_ump_stream_msg_devince_info { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 format:2; + u32 status:10; + u32 reserved:16; + /* 1 */ + u32 manufacture_id; + /* 2 */ + u8 family_lsb; + u8 family_msb; + u8 model_lsb; + u8 model_msb; + /* 3 */ + u32 sw_revision; +#else + /* 0 */ + u32 reserved:16; + u32 status:10; + u32 format:2; + u32 type:4; + /* 1 */ + u32 manufacture_id; + /* 2 */ + u8 model_msb; + u8 model_lsb; + u8 family_msb; + u8 family_lsb; + /* 3 */ + u32 sw_revision; +#endif +} __packed; + +/* UMP Stream Message: Stream Config Request / Notification (128bit) */ +struct snd_ump_stream_msg_stream_cfg { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 format:2; + u32 status:10; + u32 protocol:8; + u32 reserved:6; + u32 jrts:2; + /* 1-3 */ + u32 reserved2[3]; +#else + /* 0 */ + u32 jrts:2; + u32 reserved:6; + u32 protocol:8; + u32 status:10; + u32 format:2; + u32 type:4; + /* 1-3 */ + u32 reserved2[3]; +#endif +} __packed; + +/* UMP Stream Message: Function Block Discovery (128bit) */ +struct snd_ump_stream_msg_fb_discovery { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 format:2; + u32 status:10; + u32 function_block_id:8; + u32 filter:8; + /* 1-3 */ + u32 reserved[3]; +#else + /* 0 */ + u32 filter:8; + u32 function_block_id:8; + u32 status:10; + u32 format:2; + u32 type:4; + /* 1-3 */ + u32 reserved[3]; +#endif +} __packed; + +/* UMP Stream Message: Function Block Info Notification (128bit) */ +struct snd_ump_stream_msg_fb_info { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 format:2; + u32 status:10; + u32 active:1; + u32 function_block_id:7; + u32 reserved:2; + u32 ui_hint:2; + u32 midi_10:2; + u32 direction:2; + /* 1 */ + u32 first_group:8; + u32 num_groups:8; + u32 midi_ci_version:8; + u32 sysex8_streams:8; + /* 2-3 */ + u32 reserved2[2]; +#else + /* 0 */ + u32 direction:2; + u32 midi_10:2; + u32 ui_hint:2; + u32 reserved:2; + u32 function_block_id:7; + u32 active:1; + u32 status:10; + u32 format:2; + u32 type:4; + /* 1 */ + u32 sysex8_streams:8; + u32 midi_ci_version:8; + u32 num_groups:8; + u32 first_group:8; + /* 2-3 */ + u32 reserved2[2]; +#endif +} __packed; + +/* UMP Stream Message: Function Block Name Notification (128bit) */ +struct snd_ump_stream_msg_fb_name { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u16 type:4; + u16 format:2; + u16 status:10; + u8 function_block_id; + u8 name0; + /* 1-3 */ + u8 name[12]; +#else + /* 0 */ + u8 name0; + u8 function_block_id; + u16 status:10; + u16 format:2; + u16 type:4; + /* 1-3 */ + u8 name[12]; // FIXME: byte order +#endif +} __packed; + +/* MIDI 2.0 Stream Messages (128bit) */ +union snd_ump_stream_msg { + struct snd_ump_stream_msg_ep_discovery ep_discovery; + struct snd_ump_stream_msg_ep_info ep_info; + struct snd_ump_stream_msg_devince_info device_info; + struct snd_ump_stream_msg_stream_cfg stream_cfg; + struct snd_ump_stream_msg_fb_discovery fb_discovery; + struct snd_ump_stream_msg_fb_info fb_info; + struct snd_ump_stream_msg_fb_name fb_name; + u32 raw[4]; +}; + +#endif /* __SOUND_UMP_MSG_H */ |