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2023-01-23dt-bindings: drop type for operating-points-v2Gravatar Krzysztof Kozlowski 1-2/+1
The type for operating-points-v2 property is coming from dtschema (/schemas/opp/opp.yaml), so individual bindings can just use simple "true". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230119131033.117324-1-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring <robh@kernel.org>
2021-12-17dt-bindings: fuse: tegra: Document Tegra234 FUSEGravatar Thierry Reding 1-0/+1
Add the compatible string for the FUSE block found on the Tegra234 SoC. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: fuse: tegra: Convert to json-schemaGravatar Thierry Reding 2-42/+88
Convert the NVIDIA Tegra FUSE bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18dt-bindings: fuse: tegra: Add Tegra234 supportGravatar Thierry Reding 1-0/+1
The Tegra234 FUSE block is very similar to that on prior chips but not completely compatible. Document the new compatible string. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-17dt-bindings: fuse: tegra: Add missing compatible stringsGravatar Thierry Reding 1-2/+3
The Tegra FUSE device tree bindings haven't been updated in a while. Add compatible strings for the SoC generations that were released since the last update. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-05-04ARM: tegra: Use lower-case hexadecimal digitsGravatar Thierry Reding 1-1/+1
For consistency with other device tree content, use lower-case hexadecimal digits in register region specifications. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-02-03Documentation: DT bindings: add more Tegra chip compatible stringsGravatar Paul Walmsley 1-5/+5
Align compatible strings for several IP blocks present on Tegra chips with the latest doctrine from the DT maintainers: http://marc.info/?l=devicetree&m=142255654213019&w=2 The primary objective here is to avoid checkpatch warnings, per: http://marc.info/?l=linux-tegra&m=142201349727836&w=2 DT binding text files have been updated for the following IP blocks: - PCIe - SOR - SoC timers - AHB "gizmo" - APB_MISC - pinmux control - UART - PWM - I2C - SPI - RTC - PMC - eFuse - AHCI - HDA - XUSB_PADCTRL - SDHCI - SOC_THERM - AHUB - I2S - EHCI - USB PHY N.B. The nvidia,tegra20-timer compatible string is removed from the nvidia,tegra30-timer.txt documentation file because it's already mentioned in the nvidia,tegra20-timer.txt documentation file. This second version takes into account the following requests from Rob Herring <robherring2@gmail.com>: - Per-IP block patches have been combined into a single patch - Explicit documentation about which compatible strings are actually matched by the driver has been removed. In its place is implicit documentation that loosely follows Rob's prescribed format: "Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where <chip> is tegra30, tegra132, ..." [...] "You should attempt to document known values of <chip> if you use it" Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Dylan Reid <dgreid@chromium.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Jingchang Lu <jingchang.lu@freescale.com> Cc: John Crispin <blogic@openwrt.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mikko Perttunen <mperttunen@nvidia.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Peter Hurley <peter@hurleysoftware.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Takashi Iwai <tiwai@suse.de> Cc: Tejun Heo <tj@kernel.org> Cc: "Terje Bergström" <tbergstrom@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Zhang Rui <rui.zhang@intel.com> Cc: dri-devel@lists.freedesktop.org Cc: linux-i2c@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-pwm@vger.kernel.org Cc: linux-tegra@vger.kernel.org Acked-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
2014-07-17soc/tegra: Add efuse and apbmisc bindingsGravatar Peter De Schrijver 1-0/+40
Add efuse and apbmisc bindings for Tegra20, Tegra30, Tegra114 and Tegra124. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>