aboutsummaryrefslogtreecommitdiff
path: root/drivers/clk/sunxi-ng
AgeCommit message (Expand)AuthorFilesLines
2017-07-24clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clockGravatar Maxime Ripard 1-1/+1
2017-06-16clk: sunxi-ng: Staticize ccu_mux_helper_unapply_prediv()Gravatar Stephen Boyd 1-1/+1
2017-06-16Merge tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel...Gravatar Stephen Boyd 21-260/+1562
2017-06-14Merge tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/...Gravatar Stephen Boyd 5-4/+9
2017-06-07clk: sunxi-ng: Move all clock types to a libraryGravatar Stephen Boyd 2-132/+22
2017-06-07clk: sunxi-ng: a83t: Add support for A83T's PRCMGravatar Chen-Yu Tsai 1-0/+107
2017-06-07clk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83tGravatar Arnd Bergmann 1-0/+1
2017-06-07clk: sunxi-ng: a83t: Fix audio PLL divider offsetGravatar Chen-Yu Tsai 1-1/+1
2017-06-07clk: sunxi-ng: a83t: Fix PLL lock status register offsetGravatar Chen-Yu Tsai 1-1/+1
2017-06-07clk: sunxi-ng: Add driver for A83T CCUGravatar Chen-Yu Tsai 4-0/+998
2017-06-07clk: sunxi-ng: Support multiple variable pre-dividersGravatar Chen-Yu Tsai 9-47/+54
2017-06-07clk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR()Gravatar Wei Yongjun 1-1/+1
2017-06-07clk: sunxi-ng: sun5i: Export video PLLsGravatar Maxime Ripard 1-2/+4
2017-06-07clk: sunxi-ng: mux: Re-adjust parent rateGravatar Maxime Ripard 1-5/+28
2017-06-07clk: sunxi-ng: mux: Change pre-divider application function prototypeGravatar Maxime Ripard 5-33/+28
2017-06-07clk: sunxi-ng: mux: split out the pre-divider computation codeGravatar Maxime Ripard 1-12/+20
2017-06-07clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENTGravatar Maxime Ripard 1-13/+1
2017-06-07clk: sunxi-ng: div: Switch to divider_round_rateGravatar Maxime Ripard 1-23/+4
2017-06-07clk: sunxi-ng: Pass the parent and a pointer to the clocks round rateGravatar Maxime Ripard 6-18/+25
2017-06-07clk: sunxi-ng: explicitly include linux/spinlock.hGravatar Tobias Klauser 1-0/+1
2017-06-07clk: sunxi-ng: add support for DE2 CCUGravatar Icenowy Zheng 4-0/+294
2017-05-31clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCMGravatar Chen-Yu Tsai 1-1/+3
2017-05-31clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCMGravatar Chen-Yu Tsai 1-1/+3
2017-05-25clk: sunxi-ng: sun5i: Fix ahb_bist_clk definitionGravatar Boris Brezillon 1-1/+1
2017-05-18clk: sunxi-ng: enable SUNXI_CCU_MP for PRCMGravatar Arnd Bergmann 1-0/+1
2017-05-14clk: sunxi-ng: v3s: Fix usb otg device reset bitGravatar Yong Deng 1-1/+1
2017-05-14clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offsetGravatar Chen-Yu Tsai 1-1/+1
2017-05-10Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Gravatar Linus Torvalds 17-53/+710
2017-04-28clk: sunxi-ng: always select CCU_GATEGravatar Arnd Bergmann 1-1/+1
2017-04-21Merge tag 'sunxi-clk-for-4.12-2' of https://git.kernel.org/pub/scm/linux/kern...Gravatar Stephen Boyd 7-18/+17
2017-04-19Merge tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel...Gravatar Stephen Boyd 13-37/+695
2017-04-13clk: sunxi-ng: a80: Fix audio PLL comment not matching actual codeGravatar Chen-Yu Tsai 1-2/+1
2017-04-13clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatchGravatar Chen-Yu Tsai 2-3/+3
2017-04-13clk: sunxi-ng: use 1 as fallback for minimum multiplierGravatar Chen-Yu Tsai 4-11/+11
2017-04-13clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate changeGravatar Chen-Yu Tsai 1-0/+11
2017-04-13clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocksGravatar Chen-Yu Tsai 2-0/+61
2017-04-13clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driverGravatar Tobias Regnery 1-0/+1
2017-04-13clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLERGravatar Tobias Regnery 1-0/+1
2017-04-10clk: sunxi-ng: fix PRCM CCU CLK_NUMBER valueGravatar Icenowy Zheng 1-1/+1
2017-04-10clk: sunxi-ng: fix PRCM CCU ir clk parentGravatar Icenowy Zheng 1-1/+1
2017-04-06clk: sunxi-ng: Display index when clock registration failsGravatar Priit Laes 1-2/+2
2017-04-05clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factorGravatar Chen-Yu Tsai 1-7/+11
2017-04-05clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocksGravatar Chen-Yu Tsai 1-18/+52
2017-04-05clk: sunxi-ng: mult: Support PLL lock detectionGravatar Chen-Yu Tsai 2-0/+4
2017-04-04clk: sunxi-ng: add support for PRCM CCUsGravatar Icenowy Zheng 4-0/+247
2017-03-20clk: sunxi-ng: fix recalc_rate formula of NKMP clocksGravatar Icenowy Zheng 1-1/+1
2017-03-20clk: sunxi-ng: Fix div/mult settings for osc12M on A64Gravatar Philipp Tomsich 1-1/+1
2017-03-06clk: sunxi-ng: sun5i: Fix mux width for csi clockGravatar Priit Laes 1-1/+1
2017-03-06clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCsGravatar Peter Robinson 1-0/+8
2017-03-06clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driverGravatar Icenowy Zheng 3-9/+323