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2024-01-09cxl/events: Create common event UUID definesGravatar Ira Weiny 2-27/+27
2024-01-05Merge branch 'for-6.7/cxl' into for-6.8/cxlGravatar Dan Williams 3-26/+14
2024-01-05Merge branch 'for-6.8/cxl-misc' into for-6.8/cxlGravatar Dan Williams 1-1/+1
2024-01-05Merge branch 'for-6.8/cxl-cdat' into for-6.8/cxlGravatar Dan Williams 6-27/+44
2024-01-05cxl/events: Promote CXL event structures to a core headerGravatar Ira Weiny 1-89/+1
2024-01-05cxl: Refactor to use __free() for cxl_root allocation in cxl_endpoint_port_pr...Gravatar Dave Jiang 1-3/+2
2024-01-05cxl: Refactor to use __free() for cxl_root allocation in cxl_find_nvdimm_brid...Gravatar Dave Jiang 1-5/+3
2024-01-05cxl: Fix device reference leak in cxl_port_perf_data_calculate()Gravatar Dave Jiang 1-2/+5
2024-01-05cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Gravatar Dave Jiang 6-23/+28
2024-01-05cxl: Introduce put_cxl_root() helperGravatar Dave Jiang 2-0/+12
2024-01-04cxl/port: Fix missing target list lockGravatar Dan Williams 2-17/+7
2024-01-04cxl/port: Fix decoder initialization when nr_targets > interleave_waysGravatar Huang Ying 1-1/+1
2024-01-03cxl/region: fix x9 interleave typoGravatar Jim Harris 1-1/+1
2024-01-03cxl/trace: Pass UUID explicitly to event tracesGravatar Ira Weiny 2-18/+18
2024-01-02Merge branch 'for-6.8/cxl-cdat' into for-6.8/cxlGravatar Dan Williams 17-39/+1009
2024-01-02cxl/region: use %pap format to print resource_size_tGravatar Randy Dunlap 1-2/+2
2023-12-24cxl/region: Add dev_dbg() detail on failure to allocate HPA spaceGravatar Alison Schofield 1-2/+3
2023-12-22cxl: Check qos_class validity on memdev probeGravatar Dave Jiang 1-0/+103
2023-12-22cxl: Export sysfs attributes for memory device QoS classGravatar Dave Jiang 1-6/+61
2023-12-22cxl: Store QTG IDs and related info to the CXL memory device contextGravatar Dave Jiang 3-0/+92
2023-12-22cxl: Compute the entire CXL path latency and bandwidth dataGravatar Dave Jiang 1-1/+58
2023-12-22cxl: Add helper function that calculate performance data for downstream portsGravatar Dave Jiang 2-0/+78
2023-12-22cxl: Store the access coordinates for the generic portsGravatar Dave Jiang 2-0/+27
2023-12-22cxl: Calculate and store PCI link latency for the downstream portsGravatar Dave Jiang 5-0/+61
2023-12-22cxl: Add support for _DSM Function for retrieving QTG IDGravatar Dave Jiang 3-13/+193
2023-12-22cxl: Add callback to parse the SSLBIS subtable from CDATGravatar Dave Jiang 3-0/+104
2023-12-22cxl: Add callback to parse the DSLBIS subtable from CDATGravatar Dave Jiang 1-2/+100
2023-12-22cxl: Add callback to parse the DSMAS subtables from CDATGravatar Dave Jiang 5-0/+99
2023-12-18cxl: Fix unregister_region() callback parameter assignmentGravatar Dave Jiang 1-4/+4
2023-12-14cxl/pmu: Ensure put_device on pmu devicesGravatar Ira Weiny 1-1/+1
2023-12-08cxl/cdat: Free correct buffer on checksum errorGravatar Ira Weiny 1-7/+6
2023-12-07cxl/hdm: Fix dpa translation lockingGravatar Dan Williams 2-4/+3
2023-12-07cxl: Add Support for Get TimestampGravatar Davidlohr Bueso 2-0/+2
2023-11-29cxl/memdev: Hold region_rwsem during inject and clear poison opsGravatar Alison Schofield 1-2/+16
2023-11-29cxl/core: Always hold region_rwsem while reading poison listsGravatar Alison Schofield 2-6/+8
2023-11-22cxl/hdm: Fix a benign lockdep splatGravatar Dave Jiang 1-0/+2
2023-11-02cxl/pci: Change CXL AER support check to use native AERGravatar Terry Bowman 1-2/+2
2023-10-31cxl/hdm: Remove broken error pathGravatar Dan Williams 2-17/+10
2023-10-31cxl/hdm: Fix && vs || bugGravatar Dan Carpenter 1-1/+1
2023-10-31Merge branch 'for-6.7/cxl-commited' into cxl/nextGravatar Dan Williams 5-6/+40
2023-10-31Merge branch 'for-6.7/cxl' into cxl/nextGravatar Dan Williams 4-5/+11
2023-10-31Merge branch 'for-6.7/cxl-qtg' into cxl/nextGravatar Dan Williams 5-12/+60
2023-10-31Merge branch 'for-6.7/cxl-rch-eh' into cxl/nextGravatar Dan Williams 10-129/+406
2023-10-27cxl: Add support for reading CXL switch CDAT tableGravatar Dave Jiang 2-5/+20
2023-10-27cxl: Add checksum verification to CDAT from CXLGravatar Dave Jiang 1-7/+23
2023-10-27cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeGravatar Dave Jiang 3-0/+17
2023-10-27cxl: Add decoders_committed sysfs attribute to cxl_portGravatar Dave Jiang 1-0/+25
2023-10-27cxl: Add cxl_decoders_committed() helperGravatar Dave Jiang 5-6/+15
2023-10-27cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devmGravatar Robert Richter 3-6/+4
2023-10-27cxl/core/regs: Rename phys_addr in cxl_map_component_regs()Gravatar Robert Richter 1-3/+3
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