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2023-10-13Merge tag 'dmaengine-fix-6.6' of ↵Gravatar Linus Torvalds 8-24/+76
git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine Pull dmaengine fixes from Vinod Koul: "Driver fixes for: - stm32 dma residue calculation and chaining - stm32 mdma for setting inflight bytes, residue calculation and resume abort - channel request, channel enable and dma error in fsl_edma - runtime pm imbalance in ste_dma40 driver - deadlock fix in mediatek driver" * tag 'dmaengine-fix-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: dmaengine: fsl-edma: fix all channels requested when call fsl_edma3_xlate() dmaengine: stm32-dma: fix residue in case of MDMA chaining dmaengine: stm32-dma: fix stm32_dma_prep_slave_sg in case of MDMA chaining dmaengine: stm32-mdma: set in_flight_bytes in case CRQA flag is set dmaengine: stm32-mdma: use Link Address Register to compute residue dmaengine: stm32-mdma: abort resume if no ongoing transfer dmaengine: ste_dma40: Fix PM disable depth imbalance in d40_probe dmaengine: mediatek: Fix deadlock caused by synchronize_irq() dmaengine: idxd: use spin_lock_irqsave before wait_event_lock_irq dmaengine: fsl-edma: fix edma4 channel enable failure on second attempt dt-bindings: dmaengine: zynqmp_dma: add xlnx,bus-width required property dmaengine: fsl-dma: fix DMA error when enabling sg if 'DONE' bit is set
2023-10-09dmaengine: fsl-edma: fix all channels requested when call fsl_edma3_xlate()Gravatar Frank Li 1-2/+4
dma_get_slave_channel() increases client_count for all channels. It should only be called when a matched channel is found in fsl_edma3_xlate(). Move dma_get_slave_channel() after checking for a matched channel. Cc: stable@vger.kernel.org Fixes: 72f5801a4e2b ("dmaengine: fsl-edma: integrate v3 support") Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20231004142911.838916-1-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-09dmaengine: stm32-dma: fix residue in case of MDMA chainingGravatar Amelie Delaunay 1-3/+4
In case of MDMA chaining, DMA is configured in Double-Buffer Mode (DBM) with two periods, but if transfer has been prepared with _prep_slave_sg(), the transfer is not marked cyclic (=!chan->desc->cyclic). However, as DBM is activated for MDMA chaining, residue computation must take into account cyclic constraints. With only two periods in MDMA chaining, and no update due to Transfer Complete interrupt masked, n_sg is always 0. If DMA current memory address (depending on SxCR.CT and SxM0AR/SxM1AR) does not correspond, it means n_sg should be increased. Then, the residue of the current period is the one read from SxNDTR and should not be overwritten with the full period length. Fixes: 723795173ce1 ("dmaengine: stm32-dma: add support to trigger STM32 MDMA") Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20231004155024.2609531-2-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-09dmaengine: stm32-dma: fix stm32_dma_prep_slave_sg in case of MDMA chainingGravatar Amelie Delaunay 1-1/+3
Current Target (CT) have to be reset when starting an MDMA chaining use case, as Double Buffer mode is activated. It ensures the DMA will start processing the first memory target (pointed with SxM0AR). Fixes: 723795173ce1 ("dmaengine: stm32-dma: add support to trigger STM32 MDMA") Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20231004155024.2609531-1-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-09dmaengine: stm32-mdma: set in_flight_bytes in case CRQA flag is setGravatar Amelie Delaunay 1-5/+9
CRQA flag is set by hardware when the channel request become active and the channel is enabled. It is cleared by hardware, when the channel request is completed. So when it is set, it means MDMA is transferring bytes. This information is useful in case of STM32 DMA and MDMA chaining, especially when the user pauses DMA before stopping it, to trig one last MDMA transfer to get the latest bytes of the SRAM buffer to the destination buffer. STM32 DCMI driver can then use this to know if the last MDMA transfer in case of chaining is done. Fixes: 696874322771 ("dmaengine: stm32-mdma: add support to be triggered by STM32 DMA") Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20231004163531.2864160-3-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-09dmaengine: stm32-mdma: use Link Address Register to compute residueGravatar Amelie Delaunay 1-4/+11
Current implementation relies on curr_hwdesc index. But to keep this index up to date, Block Transfer interrupt (BTIE) has to be enabled. If it is not, curr_hwdesc is not updated, and then residue is not reliable. Rely on Link Address Register instead. And disable BTIE interrupt in stm32_mdma_setup_xfer() because it is no more needed in case of _prep_slave_sg() to maintain curr_hwdesc up to date. It avoids extra interrupts and also ensures a reliable residue. These improvements are required for STM32 DCMI camera capture use case, which need STM32 DMA and MDMA chaining for good performance. Fixes: 696874322771 ("dmaengine: stm32-mdma: add support to be triggered by STM32 DMA") Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20231004163531.2864160-2-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-09dmaengine: stm32-mdma: abort resume if no ongoing transferGravatar Amelie Delaunay 1-0/+4
chan->desc can be null, if transfer is terminated when resume is called, leading to a NULL pointer when retrieving the hwdesc. To avoid this case, check that chan->desc is not null and channel is disabled (transfer previously paused or terminated). Fixes: a4ffb13c8946 ("dmaengine: Add STM32 MDMA driver") Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20231004163531.2864160-1-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-09dmaengine: ste_dma40: Fix PM disable depth imbalance in d40_probeGravatar Zhang Shurong 1-0/+1
The pm_runtime_enable will increase power disable depth. Thus a pairing decrement is needed on the error handling path to keep it balanced according to context. We fix it by calling pm_runtime_disable when error returns. Signed-off-by: Zhang Shurong <zhang_shurong@foxmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/tencent_DD2D371DB5925B4B602B1E1D0A5FA88F1208@qq.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-04dmaengine: mediatek: Fix deadlock caused by synchronize_irq()Gravatar Duoming Zhou 1-2/+1
The synchronize_irq(c->irq) will not return until the IRQ handler mtk_uart_apdma_irq_handler() is completed. If the synchronize_irq() holds a spin_lock and waits the IRQ handler to complete, but the IRQ handler also needs the same spin_lock. The deadlock will happen. The process is shown below: cpu0 cpu1 mtk_uart_apdma_device_pause() | mtk_uart_apdma_irq_handler() spin_lock_irqsave() | | spin_lock_irqsave() //hold the lock to wait | synchronize_irq() | This patch reorders the synchronize_irq(c->irq) outside the spin_lock in order to mitigate the bug. Fixes: 9135408c3ace ("dmaengine: mediatek: Add MediaTek UART APDMA support") Signed-off-by: Duoming Zhou <duoming@zju.edu.cn> Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> Link: https://lore.kernel.org/r/20230806032511.45263-1-duoming@zju.edu.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-04dmaengine: ti: k3-udma-glue: clean up k3_udma_glue_tx_get_irq() returnGravatar Dan Carpenter 1-0/+3
The k3_udma_glue_tx_get_irq() function currently returns negative error codes on error, zero on error and positive values for success. This complicates life for the callers who need to propagate the error code. Also GCC will not warn about unsigned comparisons when you check: if (unsigned_irq <= 0) All the callers have been fixed now but let's just make this easy going forward. Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2023-10-04dmaengine: idxd: use spin_lock_irqsave before wait_event_lock_irqGravatar Rex Zhang 1-2/+3
In idxd_cmd_exec(), wait_event_lock_irq() explicitly calls spin_unlock_irq()/spin_lock_irq(). If the interrupt is on before entering wait_event_lock_irq(), it will become off status after wait_event_lock_irq() is called. Later, wait_for_completion() may go to sleep but irq is disabled. The scenario is warned in might_sleep(). Fix it by using spin_lock_irqsave() instead of the primitive spin_lock() to save the irq status before entering wait_event_lock_irq() and using spin_unlock_irqrestore() instead of the primitive spin_unlock() to restore the irq status before entering wait_for_completion(). Before the change: idxd_cmd_exec() { interrupt is on spin_lock() // interrupt is on wait_event_lock_irq() spin_unlock_irq() // interrupt is enabled ... spin_lock_irq() // interrupt is disabled spin_unlock() // interrupt is still disabled wait_for_completion() // report "BUG: sleeping function // called from invalid context... // in_atomic() irqs_disabled()" } After applying spin_lock_irqsave(): idxd_cmd_exec() { interrupt is on spin_lock_irqsave() // save the on state // interrupt is disabled wait_event_lock_irq() spin_unlock_irq() // interrupt is enabled ... spin_lock_irq() // interrupt is disabled spin_unlock_irqrestore() // interrupt is restored to on wait_for_completion() // No Call trace } Fixes: f9f4082dbc56 ("dmaengine: idxd: remove interrupt disable for cmd_lock") Signed-off-by: Rex Zhang <rex.zhang@intel.com> Signed-off-by: Lijun Pan <lijun.pan@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Fenghua Yu <fenghua.yu@intel.com> Link: https://lore.kernel.org/r/20230916060619.3744220-1-rex.zhang@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-09-28dmaengine: fsl-edma: fix edma4 channel enable failure on second attemptGravatar Frank Li 1-2/+8
When attempting to start DMA for the second time using fsl_edma3_enable_request(), channel never start. CHn_MUX must have a unique value when selecting a peripheral slot in the channel mux configuration. The only value that may overlap is source 0. If there is an attempt to write a mux configuration value that is already consumed by another channel, a mux configuration of 0 (SRC = 0) will be written. Check CHn_MUX before writing in fsl_edma3_enable_request(). Fixes: 72f5801a4e2b ("dmaengine: fsl-edma: integrate v3 support") Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230823182635.2618118-1-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-09-28dmaengine: fsl-dma: fix DMA error when enabling sg if 'DONE' bit is setGravatar Frank Li 3-3/+28
In eDMAv3, clearing 'DONE' bit (bit 30) of CHn_CSR is required when enabling scatter-gather (SG). eDMAv4 does not require this change. Cc: stable@vger.kernel.org Fixes: 72f5801a4e2b ("dmaengine: fsl-edma: integrate v3 support") Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230921144652.3259813-1-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-09-03Merge tag 'dmaengine-6.6-rc1' of ↵Gravatar Linus Torvalds 64-2771/+765
git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine Pull dmaengine updates from Vinod Koul: "New controller support and updates to drivers. New support: - Qualcomm SM6115 and QCM2290 dmaengine support - at_xdma support for microchip,sam9x7 controller Updates: - idxd updates for wq simplification and ats knob updates - fsl edma updates for v3 support - Xilinx AXI4-Stream control support - Yaml conversion for bcm dma binding" * tag 'dmaengine-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (53 commits) dmaengine: fsl-edma: integrate v3 support dt-bindings: fsl-dma: fsl-edma: add edma3 compatible string dmaengine: fsl-edma: move tcd into struct fsl_dma_chan dmaengine: fsl-edma: refactor chan_name setup and safety dmaengine: fsl-edma: move clearing of register interrupt into setup_irq function dmaengine: fsl-edma: refactor using devm_clk_get_enabled dmaengine: fsl-edma: simply ATTR_DSIZE and ATTR_SSIZE by using ffs() dmaengine: fsl-edma: move common IRQ handler to common.c dmaengine: fsl-edma: Remove enum edma_version dmaengine: fsl-edma: transition from bool fields to bitmask flags in drvdata dmaengine: fsl-edma: clean up EXPORT_SYMBOL_GPL in fsl-edma-common.c dmaengine: fsl-edma: fix build error when arch is s390 dmaengine: idxd: Fix issues with PRS disable sysfs knob dmaengine: idxd: Allow ATS disable update only for configurable devices dmaengine: xilinx_dma: Program interrupt delay timeout dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical usecase dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit dmaengine: xilinx_dma: Increase AXI DMA transaction segment count dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property ...
2023-08-22dmaengine: fsl-edma: integrate v3 supportGravatar Frank Li 3-23/+453
Significant alterations have been made to the EDMA v3's register layout. Now, each channel possesses a separate address space, encapsulating all channel-related controls and statuses, including IRQs. There are changes in bit position definitions as well. However, the fundamental control flow remains analogous to the previous versions. EDMA v3 was utilized in imx8qm, imx93, and will be in forthcoming chips. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-13-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: move tcd into struct fsl_dma_chanGravatar Frank Li 4-28/+42
Relocates the tcd into the fsl_dma_chan structure. This adjustment reduces the need to reference back to fsl_edma_engine, paving the way for EDMA V3 support. Unified the edma_writel and edma_writew functions for accessing TCD (Transfer Control Descriptor) registers. A new macro is added that can automatically detect whether a 32-bit or 16-bit access should be used based on the structure field definition. This provide better support 64-bit TCD with future v5 version. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202305271951.gmRobs3a-lkp@intel.com/ Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-11-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: refactor chan_name setup and safetyGravatar Frank Li 2-3/+4
Relocated the setup of chan_name from setup_irq() to fsl_chan init. This change anticipates its future use in various locations. For increased safety, sprintf has been replaced with snprintf. In addition, The size of the fsl_chan->name[] array was expanded from 16 to 32. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-10-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: move clearing of register interrupt into setup_irq functionGravatar Frank Li 1-1/+4
This accommodates differences in the register layout of EDMA v3 by moving the clearing of register interrupts into the platform-specific set_irq function. This should ensure better compatibility with EDMA v3. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-9-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: refactor using devm_clk_get_enabledGravatar Frank Li 1-17/+2
Use devm_clk_get_enabled in probe code to reduce error checks, thereby enhancing readability Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-8-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: simply ATTR_DSIZE and ATTR_SSIZE by using ffs()Gravatar Frank Li 2-23/+8
Removes all ATTR_DSIZE_*BIT(BYTE) and ATTR_SSIZE_*BIT(BYTE) definitions in edma. Uses ffs() instead, as it gives identical results. This simplifies the code and avoids adding more similar definitions in future V3 version. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-7-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: move common IRQ handler to common.cGravatar Frank Li 4-56/+37
Move the common part of IRQ handler from fsl-edma-main.c and mcf-edma-main.c to fsl-edma-common.c. This eliminates redundant code, as the both files contains mostly identical code. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-6-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: Remove enum edma_versionGravatar Frank Li 4-41/+26
The enum edma_version, which defines v1, v2, and v3, is a software concept used to distinguish IP differences. However, it is not aligned with the chip reference manual. According to the 7ulp reference manual, it should be edma2. In the future, there will be edma3, edma4, and edma5, which could cause confusion. To avoid this confusion, remove the edma_version and instead use drvdata->flags to distinguish the IP difference. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-5-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: transition from bool fields to bitmask flags in drvdataGravatar Frank Li 3-6/+7
Replace individual bool fields with bitmask flags within drvdata. This will facilitate future extensions, making it easier to add more flags to accommodate new versions of the edma IP. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-4-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: clean up EXPORT_SYMBOL_GPL in fsl-edma-common.cGravatar Frank Li 4-19/+4
Exported functions in fsl-edma-common.c are only used within fsl-edma.c and mcf-edma.c. Global export is unnecessary. This commit removes all EXPORT_SYMBOL_GPL in fsl-edma-common.c, and renames fsl-edma.c and mcf-edma.c to maintain the same final module names as before, thereby simplifying the codebase. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-3-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: fix build error when arch is s390Gravatar Frank Li 1-0/+1
fixed build error reported by kernel test robot. >> s390-linux-ld: fsl-edma-main.c:(.text+0xf4c): undefined reference to `devm_platform_ioremap_resource' s390-linux-ld: drivers/dma/idma64.o: in function `idma64_platform_probe': Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202306210131.zaHVasxz-lkp@intel.com/ Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-2-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: idxd: Fix issues with PRS disable sysfs knobGravatar Fenghua Yu 1-2/+2
There are two issues in the current PRS disable sysfs store function wq_prs_disable_store(): 1. Since PRS disable knob is invisible if PRS disable is not supported in WQ, it's redundant to check PRS support again in the store function again. Remove the redundant PRS support check. 2. Since PRS disable is read-only when the device is not configurable, PRS disable cannot be changed on the device. Add device configurable check in the store function. Fixes: f2dc327131b5 ("dmaengine: idxd: add per wq PRS disable") Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230811012635.535413-2-fenghua.yu@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: idxd: Allow ATS disable update only for configurable devicesGravatar Fenghua Yu 1-0/+4
ATS disable status in a WQ is read-only if the device is not configurable. This change ensures that the ATS disable attribute can be modified via sysfs only on configurable devices. Fixes: 92de5fa2dc39 ("dmaengine: idxd: add ATS disable knob for work queues") Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230811012635.535413-1-fenghua.yu@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: xilinx_dma: Program interrupt delay timeoutGravatar Radhey Shyam Pandey 1-9/+11
Program IRQDelay for AXI DMA. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. It enables dmaengine to respond in real-time even though interrupt coalescing is configured. It also remove the placeholder for delay interrupt and merge it with frame completion interrupt. Since by default interrupt delay timeout is disabled this feature addition has no functional impact on VDMA, MCDMA and CDMA IP's. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/1691387509-2113129-8-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical usecaseGravatar Radhey Shyam Pandey 1-1/+1
Schedule tasklet with high priority to ensure that callback processing is prioritized. It improves throughput for netdev dma clients. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/1691387509-2113129-7-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: xilinx_dma: Freeup active list based on descriptor completion bitGravatar Radhey Shyam Pandey 1-0/+9
AXIDMA IP in SG mode sets completion bit to 1 when the transfer is completed. Read this bit to move descriptor from active list to the done list. This feature is needed when interrupt delay timeout and IRQThreshold is enabled i.e Dly_IrqEn is triggered w/o completing interrupt threshold. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/1691387509-2113129-6-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: xilinx_dma: Increase AXI DMA transaction segment countGravatar Radhey Shyam Pandey 1-1/+1
Increase AXI DMA transaction segments count to ensure that even in high load we always get a free segment in prepare descriptor for a DMA_SLAVE transaction. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/1691387509-2113129-5-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma clientGravatar Radhey Shyam Pandey 1-0/+37
Read DT property to check if AXI DMA is connected to streaming IP i.e axiethernet. If connected i.e xlnx,axistream-connected property is present in the dma node then pass AXI4-Stream control words to dma client using metadata_ops dmaengine API. If not connected then driver won't support metadata_ops dmaengine API and continue to support all legacy usecases. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/1691387509-2113129-4-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: ioatdma: use pci_dev_id() to simplify the codeGravatar Jialin Zhang 1-1/+1
PCI core API pci_dev_id() can be used to get the BDF number for a pci device. We don't need to compose it mannually. Use pci_dev_id() to simplify the code a little bit. Signed-off-by: Jialin Zhang <zhangjialin11@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230815023821.3518007-1-zhangjialin11@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: ioat: fixing the wrong dma_dev->chancntGravatar Yajun Deng 2-9/+11
The chancnt would be updated in __dma_async_device_channel_register(), but it was assigned in ioat_enumerate_channels(). Therefore chancnt has the wrong value. Add chancnt member to the struct ioatdma_device, ioat_dma->chancnt is used in ioat, dma_dev->chancnt is used in dmaengine. Signed-off-by: Yajun Deng <yajun.deng@linux.dev> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230815061151.2724474-1-yajun.deng@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: Simplify dma_async_device_register()Gravatar Yajun Deng 1-62/+20
There are a lot of duplicate codes for checking if the dma has some capability. Define a temporary macro that is used to check if the dma claims some capability and if the corresponding function is implemented. Signed-off-by: Yajun Deng <yajun.deng@linux.dev> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230815072346.2798927-1-yajun.deng@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: fsl-edma: use struct_size() helperGravatar Yu Liao 1-4/+3
Make use of the struct_size() helper instead of an open-coded version, in order to avoid any potential type mistakes or integer overflows that, in the worst scenario, could lead to heap overflows. Signed-off-by: Yu Liao <liaoyu15@huawei.com> Link: https://lore.kernel.org/r/20230821073600.4078584-1-liaoyu15@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21Merge branches 'apple/dart', 'arm/mediatek', 'arm/renesas', 'arm/rockchip', ↵Gravatar Joerg Roedel 5-38/+76
'arm/smmu', 'unisoc', 'x86/vt-d', 'x86/amd' and 'core' into next
2023-08-21dmaengine: mcf-edma: Use struct_size()Gravatar Christophe JAILLET 1-4/+3
Use struct_size() instead of hand writing it. This is less verbose and more informative. 'mcf_chan' is now unused and can be removed. In fact, it is shadowed by another variable in the 'for' loop below. Keep this one. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/97c2bb1c9b69d0739da3762a7752ae6582c4ad02.1683390112.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: lgm: Use builtin_platform_driver macro to simplify the codeGravatar Li Zetao 1-6/+1
Use the builtin_platform_driver macro to simplify the code, which is the same as declaring with device_initcall(). Signed-off-by: Li Zetao <lizetao1@huawei.com> Acked-by: Peter Harliman Liem <pliem@maxlinear.com> Link: https://lore.kernel.org/r/20230815080250.1089589-1-lizetao1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: ste_dma40: Add missing IRQ check in d40_probeGravatar ruanjinjie 1-0/+4
Check for the return value of platform_get_irq(): if no interrupt is specified, it wouldn't make sense to call request_irq(). Fixes: 8d318a50b3d7 ("DMAENGINE: Support for ST-Ericssons DMA40 block v3") Signed-off-by: Ruan Jinjie <ruanjinjie@huawei.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230724144108.2582917-1-ruanjinjie@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: owl-dma: fix clang -Wvoid-pointer-to-enum-cast warningGravatar Justin Stitt 1-1/+1
When building with clang 18 I see the following warning: | drivers/dma/owl-dma.c:1119:14: warning: cast to smaller integer type | 'enum owl_dma_id' from 'const void *' [-Wvoid-pointer-to-enum-cast] | 1119 | od->devid = (enum owl_dma_id)of_device_get_match_data(&pdev->dev); This is due to the fact that `of_device_get_match_data()` returns a void* while `enum owl_dma_id` has the size of an int. Cast result of `of_device_get_match_data()` to a uintptr_t to silence the above warning for clang builds using W=1 Link: https://github.com/ClangBuiltLinux/linux/issues/1910 Reported-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Justin Stitt <justinstitt@google.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/r/20230816-void-drivers-dma-owl-dma-v1-1-a0a5e085e937@google.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: idxd: Remove unused declarationsGravatar Yue Haibing 1-5/+0
Commit c05257b5600b ("dmanegine: idxd: open code the dsa_drv registration") removed idxd_{un}register_driver() definitions but not the declarations. Commit 034b3290ba25 ("dmaengine: idxd: create idxd_device sub-driver") declared idxd_{un}register_idxd_drv() but never implemented it. Commit 8f47d1a5e545 ("dmaengine: idxd: connect idxd to dmaengine subsystem") declared idxd_parse_completion_status() but never implemented it. Signed-off-by: Yue Haibing <yuehaibing@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Fenghua Yu <fenghua.yu@intel.com> Link: https://lore.kernel.org/r/20230817114135.50264-1-yuehaibing@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-09dmaengine/idxd: Re-enable kernel workqueue under DMA APIGravatar Jacob Pan 5-38/+76
Kernel workqueues were disabled due to flawed use of kernel VA and SVA API. Now that we have the support for attaching PASID to the device's default domain and the ability to reserve global PASIDs from SVA APIs, we can re-enable the kernel work queues and use them under DMA API. We also use non-privileged access for in-kernel DMA to be consistent with the IOMMU settings. Consequently, interrupt for user privilege is enabled for work completion IRQs. Link: https://lore.kernel.org/linux-iommu/20210511194726.GP1002214@nvidia.com/ Tested-by: Tony Zhu <tony.zhu@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Link: https://lore.kernel.org/r/20230802212427.1497170-9-jacob.jun.pan@linux.intel.com Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2023-08-07dmaengine: xilinx: xdma: Fix typoGravatar Miquel Raynal 1-1/+1
Probably a copy/paste error with the previous block, here we are actually managing C2H IRQs. Fixes: 17ce252266c7 ("dmaengine: xilinx: xdma: Add xilinx xdma driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230731101442.792514-3-miquel.raynal@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-07dmaengine: xilinx: xdma: Fix interrupt vector settingGravatar Miquel Raynal 1-0/+2
A couple of hardware registers need to be set to reflect which interrupts have been allocated to the device. Each register is 32-bit wide and can receive four 8-bit values. If we provide any other interrupt number than four, the irq_num variable will never be 0 within the while check and the while block will loop forever. There is an easy way to prevent this: just break the for loop when we reach "irq_num == 0", which anyway means all interrupts have been processed. Cc: stable@vger.kernel.org Fixes: 17ce252266c7 ("dmaengine: xilinx: xdma: Add xilinx xdma driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://lore.kernel.org/r/20230731101442.792514-2-miquel.raynal@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-07dmaengine: owl-dma: Modify mismatched function nameGravatar Zhang Jianhua 1-1/+1
No functional modification involved. drivers/dma/owl-dma.c:208: warning: expecting prototype for struct owl_dma_pchan. Prototype was for struct owl_dma_vchan instead HDRTEST usr/include/sound/asequencer.h Fixes: 47e20577c24d ("dmaengine: Add Actions Semi Owl family S900 DMA driver") Signed-off-by: Zhang Jianhua <chris.zjh@huawei.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/r/20230722153244.2086949-1-chris.zjh@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-07dmaengine: idxd: Clear PRS disable flag when disabling IDXD deviceGravatar Fenghua Yu 1-3/+1
Disabling IDXD device doesn't reset Page Request Service (PRS) disable flag to its initial value 0. This may cause user confusion because once PRS is disabled user will see PRS still remains the previous setting (i.e. disabled) via sysfs interface even after the device is disabled. To eliminate user confusion, reset PRS disable flag to ensure that the PRS flag bit reflects correct state after the device is disabled. Additionally, simplify the code by setting wq->flags to 0, which clears all flag bits, including any future additions. Fixes: f2dc327131b5 ("dmaengine: idxd: add per wq PRS disable") Tested-by: Tony Zhu <tony.zhu@intel.com> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230712193505.3440752-1-fenghua.yu@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-07dmaengine: pl330: Return DMA_PAUSED when transaction is pausedGravatar Ilpo Järvinen 1-2/+16
pl330_pause() does not set anything to indicate paused condition which causes pl330_tx_status() to return DMA_IN_PROGRESS. This breaks 8250 DMA flush after the fix in commit 57e9af7831dc ("serial: 8250_dma: Fix DMA Rx rearm race"). The function comment for pl330_pause() claims pause is supported but resume is not which is enough for 8250 DMA flush to work as long as DMA status reports DMA_PAUSED when appropriate. Add PAUSED state for descriptor and mark BUSY descriptors with PAUSED in pl330_pause(). Return DMA_PAUSED from pl330_tx_status() when the descriptor is PAUSED. Reported-by: Richard Tresidder <rtresidd@electromag.com.au> Tested-by: Richard Tresidder <rtresidd@electromag.com.au> Fixes: 88987d2c7534 ("dmaengine: pl330: add DMA_PAUSE feature") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/linux-serial/f8a86ecd-64b1-573f-c2fa-59f541083f1a@electromag.com.au/ Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://lore.kernel.org/r/20230526105434.14959-1-ilpo.jarvinen@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-07dmaengine: mcf-edma: Fix a potential un-allocated memory accessGravatar Christophe JAILLET 1-6/+7
When 'mcf_edma' is allocated, some space is allocated for a flexible array at the end of the struct. 'chans' item are allocated, that is to say 'pdata->dma_channels'. Then, this number of item is stored in 'mcf_edma->n_chans'. A few lines later, if 'mcf_edma->n_chans' is 0, then a default value of 64 is set. This ends to no space allocated by devm_kzalloc() because chans was 0, but 64 items are read and/or written in some not allocated memory. Change the logic to define a default value before allocating the memory. Fixes: e7a3ff92eaf1 ("dmaengine: fsl-edma: add ColdFire mcf5441x edma support") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/f55d914407c900828f6fad3ea5fa791a5f17b9a4.1685172449.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-02dmaengine: ep93xx: Use struct_size()Gravatar Christophe JAILLET 1-3/+1
Use struct_size() instead of hand-writing it, when allocating a structure with a flex array. This is less verbose, more robust and more informative. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/36fa11d95b448b5f3f1677da41fe35b9e2751427.1690041500.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
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