aboutsummaryrefslogtreecommitdiff
path: root/drivers/phy/cadence
AgeCommit message (Collapse)AuthorFilesLines
2021-05-31phy: cadence: Sierra: Fix error return code in cdns_sierra_phy_probe()Gravatar Wang Wensheng 1-0/+1
Fix to return a negative error code from the error handling case instead of 0, as done elsewhere in this function. Fixes: a43f72ae136a ("phy: cadence: Sierra: Change MAX_LANES of Sierra to 16") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wang Wensheng <wangwensheng4@huawei.com> Link: https://lore.kernel.org/r/20210517015749.127799-1-wangwensheng4@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence-torrent: Add delay for PIPE clock to be stableGravatar Kishon Vijay Abraham I 1-0/+9
The Torrent spec specifies delay of 660.5us after phy_reset is asserted by the controller. To be on the safe side provide a delay of 5ms to 10ms in ->phy_on() callback where the SERDES is already configured in bootloader. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210330110138.24356-6-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence-torrent: Explicitly request exclusive reset controlGravatar Kishon Vijay Abraham I 1-1/+1
No functional change. Since the reset controls obtained in Torrent is exclusively used by the Torrent device, use exclusive reset control request API calls. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210330110138.24356-5-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence-torrent: Do not configure SERDES if it's already configuredGravatar Kishon Vijay Abraham I 1-10/+22
Do not configure torrent SERDES if it's already configured. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210330110138.24356-4-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence-torrent: Group reset APIs and clock APIsGravatar Kishon Vijay Abraham I 1-31/+53
No functional change intended. Group reset APIs and clock APIs in preparation for adding support to skip configuration if the SERDES is already configured by bootloader. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210330110138.24356-3-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Enable pll_cmnlc and pll_cmnlc1 clocksGravatar Kishon Vijay Abraham I 1-3/+37
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them. This will enable REFRCV/1 in case the pll_cmnlc/1 takes input from REFRCV/1 respectively. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-14-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)Gravatar Kishon Vijay Abraham I 2-3/+265
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's possible to select one of these two inputs from device tree. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-13-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callbackGravatar Kishon Vijay Abraham I 1-0/+3
commit 44d30d622821 ("phy: cadence: Add driver for Sierra PHY") enabled the clock in probe and failed to disable in remove callback. Add missing clk_disable_unprepare() in cdns_sierra_phy_remove(). Fixes: 44d30d622821 ("phy: cadence: Add driver for Sierra PHY") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210319124128.13308-11-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"Gravatar Kishon Vijay Abraham I 1-10/+15
Instead of having separate structure members for each input clock, add an array for the input clocks within "struct cdns_sierra_phy". This is in preparation for adding more input clocks required for supporting additional clock combination. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-10-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence-torrent: Use a common header file for Cadence SERDESGravatar Kishon Vijay Abraham I 1-1/+1
No functional change. In order to have a single header file for all Cadence SERDES move phy-cadence-torrent.h to phy-cadence.h. This is in preparation for adding Cadence Sierra SERDES specific macros. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210319124128.13308-9-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Explicitly request exclusive reset controlGravatar Kishon Vijay Abraham I 1-2/+2
No functional change. Since the reset controls obtained in Sierra is exclusively used by the Sierra device, use exclusive reset control request API calls. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20210319124128.13308-8-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Move all reset_control_get*() to a separate functionGravatar Kishon Vijay Abraham I 1-11/+25
No functional change. Group devm_reset_control_get() and devm_reset_control_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20210319124128.13308-7-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Move all clk_get_*() to a separate functionGravatar Kishon Vijay Abraham I 1-22/+35
No functional change. Group all devm_clk_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-6-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodesGravatar Kishon Vijay Abraham I 1-0/+4
Cadence Sierra PHY driver registers PHY using devm_phy_create() for all sub-nodes of Sierra device tree node. However Sierra device tree node can have sub-nodes for the various clocks in addtion to the PHY. Use devm_phy_create() only for nodes with name "phy" (or "link" for old device tree) which represent the actual PHY. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-4-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Fix PHY power_on sequenceGravatar Kishon Vijay Abraham I 1-1/+6
Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") de-asserts PHY_RESET even before the configurations are loaded in phy_init(). However PHY_RESET should be de-asserted only after all the configurations has been initialized, instead of de-asserting in probe. Fix it here. Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Cc: <stable@vger.kernel.org> # v5.4+ Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20210319124128.13308-2-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: cadence-torrent: Update PCIe + USB config for correct PLL1 clockGravatar Swapnil Jakhade 1-16/+31
Update PCIe + USB register sequences for correct PLL1 clock configuration. Also, update sequences for other USB configurations with dependent changes. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/1614838096-32291-5-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: cadence-torrent: Update SGMII/QSGMII configuration specific to TIGravatar Kishon Vijay Abraham I 1-14/+44
Update SGMII/QSGMII configuration specific to TI. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1614838096-32291-4-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: cadence-torrent: Update PCIe + QSGMII config for correct PLL1 clockGravatar Swapnil Jakhade 1-28/+49
For PCIe + QSGMII configuration where QSGMII was using PLL1 and was expecting 10GHz clock, configuration was giving 8GHz clock. Update register sequences to get correct PLL1 configuration. Also, update single link PCIe and single link SGMII/QSGMII configurations with related changes. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/1614838096-32291-2-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: cadence-torrent: Add support to drive refclk outGravatar Kishon Vijay Abraham I 2-3/+186
cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external reference clock. cmn_refclk_<p/m> can also be configured to output the reference clock. Model this derived reference clock as a "clock" so that platforms like AM642 EVM can enable it. This is used by PCIe to use the same refclk both in local SERDES and remote device. Add support here to drive refclk out. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210310120840.16447-7-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13phy: cadence-torrent: Fix error code in cdns_torrent_phy_probe()Gravatar Dan Carpenter 1-0/+1
This error path should return -EINVAL, but currently it returns success. Fixes: d09945eacad0 ("phy: cadence-torrent: Check total lane count for all subnodes is within limit") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/X9s7Wxq+b6ls0q7o@mwanda Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: cadence: convert to devm_platform_ioremap_resourceGravatar Chunfeng Yun 3-9/+3
Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Peter Chen <peter.chen@nxp.com> Link: https://lore.kernel.org/r/1604642930-29019-4-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add USB + SGMII/QSGMII multilink configurationGravatar Swapnil Jakhade 1-0/+254
Add USB + SGMII/QSGMII multilink configuration sequences. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-14-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add PCIe + USB multilink configurationGravatar Swapnil Jakhade 1-0/+216
Add PCIe + USB Unique SSC multilink configuration sequences. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-13-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add single link USB register sequencesGravatar Swapnil Jakhade 1-1/+259
Add support for single link USB configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-12-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add single link SGMII/QSGMII register sequencesGravatar Swapnil Jakhade 1-0/+89
Add support for single link SGMII/QSGMII configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-11-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_valsGravatar Swapnil Jakhade 1-4/+18
Include PHY_PLL_CFG as a first register value to configure in link_cmn_vals array values. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-10-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add PHY link configuration sequences for single linkGravatar Swapnil Jakhade 1-0/+44
Add support to configure link_cmn_vals and xcvr_diag_vals in case of single link PHY configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-9-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add clk changes for multilink configurationGravatar Swapnil Jakhade 1-24/+17
Prepare and enable clock in probe instead of phy_init. Also, remove phy_exit callback. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-8-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Update PHY reset for multilink configurationGravatar Swapnil Jakhade 1-7/+21
For multilink configuration, deassert PHY and link reset after PHY registers are configured in probe and only check link status in power_on callback. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-7-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add support for PHY multilink configurationGravatar Swapnil Jakhade 1-26/+757
Added support for multilink configuration of Torrent PHY. Currently, maximum two links are supported. In case of multilink configuration, PHY needs to be configured for both the protocols simultaneously at the beginning as per the requirement of Torrent PHY. Also, register sequences for PCIe + SGMII/QSGMII Unique SSC PHY multilink configurations are added. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-6-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add PHY APB reset supportGravatar Swapnil Jakhade 1-0/+13
Add support for PHY APB reset and make it optional. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-4-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Check cmn_ready assertion during PHY power onGravatar Swapnil Jakhade 1-1/+30
Check if cmn_ready is set after both PLL0 and PLL1 are locked. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-3-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add single link PCIe supportGravatar Swapnil Jakhade 1-30/+266
Add single link PCIe register sequences in Torrent PHY driver. Also, add support for getting SSC type from DT. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-2-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Check total lane count for all subnodes is within limitGravatar Swapnil Jakhade 1-4/+15
Add checking if total number of lanes for all subnodes is not greater than number of lanes supported by PHY. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-6-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Add separate regmap functions for torrent and DPGravatar Swapnil Jakhade 1-33/+66
Added separate functions for regmap initialization of torrent PHY generic registers and DP specific registers. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-5-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Enable support for multiple subnodesGravatar Swapnil Jakhade 1-15/+0
Enable support for multiple subnodes in torrent PHY to include multi-link combinations. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-4-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Use devm_platform_ioremap_resource() to get reg addressesGravatar Swapnil Jakhade 1-6/+2
Use devm_platform_ioremap_resource() to get register addresses instead of boilerplate code. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-3-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18phy: cadence-torrent: Use of_device_get_match_data() to get driver dataGravatar Swapnil Jakhade 1-8/+5
Use of_device_get_match_data() to get driver data instead of boilerplate code. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-2-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-16phy: cadence: torrent: Constify regmap_config structsGravatar Rikard Falkeborn 1-6/+6
The regmap_config structs are never modified and can be made const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200912204639.501669-4-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-16phy: cadence: salvo: Constify cdns_nxp_sequence_pairGravatar Rikard Falkeborn 1-3/+3
cdns_nxp_sequence_pair[] are never modified and can be made const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Reviewed-by: Peter Chen <peter.chen@nxp.com> Link: https://lore.kernel.org/r/20200912204639.501669-3-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-16phy: cadence: Sierra: Constify static structsGravatar Rikard Falkeborn 1-12/+12
The static cdns_reg_pairs and regmap_config structs are not modified and can be made const. This allows the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200912204639.501669-2-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-16Merge branch 'topic/phy_attrs' into nextGravatar Vinod Koul 1-0/+4
2020-09-16phy: cadence-torrent: Set Torrent PHY attributesGravatar Swapnil Jakhade 1-0/+4
Set Torrent PHY attributes bus_width, max_link_rate and mode for DisplayPort. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/1599805114-22063-3-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-08-31phy: cadence: salvo: Constify cdns_salvo_phy_opsGravatar Rikard Falkeborn 1-1/+1
The only usage is to pass its address to devm_phy_create() which takes a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200823220025.17588-2-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-07-13phy: cadence: salvo: fix wrong bit definitionGravatar Peter Chen 1-1/+1
It fixes RX detect wakeup using USB3 device, otherwise, the USB3 device can't wakeup USB PHY when the PHY is in 32Khz clock. Fixes: 50d35aa8c15f ("phy: cadence: salvo: add salvo phy driver") Signed-off-by: Peter Chen <peter.chen@nxp.com> Link: https://lore.kernel.org/r/20200703064600.14181-1-peter.chen@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-18phy: cadence: sierra: Fix for USB3 U1/U2 stateGravatar Sanket Parmar 1-13/+14
Updated values of USB3 related Sierra PHY registers. This change fixes USB3 device disconnect issue observed while enternig U1/U2 state. Signed-off-by: Sanket Parmar <sparmar@cadence.com> Link: https://lore.kernel.org/r/1589804053-14302-1-git-send-email-sparmar@cadence.com Reviewed-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-15phy: phy-cadence-salvo: add phy .init APIGravatar Peter Chen 1-1/+11
The .init is used for one-time PHY's initialization, and .power_on is called many times during the device lifecycle. Signed-off-by: Peter Chen <peter.chen@nxp.com> Link: https://lore.kernel.org/r/20200513125605.5545-1-peter.chen@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-07phy: cadence: salvo: add salvo phy driverGravatar Peter Chen 3-0/+325
Cadence SALVO PHY is a 28nm product, and is only used for USB3 & USB2. According to the Cadence, this PHY is a legacy Module, and Sierra and Torrent are later evolutions from it, and their sequence overlap is minimal, meaning we cannot reuse either (Sierra & Torrent) of the PHY drivers. Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: cadence-torrent: Add support for subnode bindingsGravatar Swapnil Jakhade 1-75/+217
Implement single link subnode support to the phy driver. Add reset support including PHY reset and individual lane reset. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: cadence-torrent: Add platform dependent initialization structureGravatar Swapnil Jakhade 1-0/+9
Add platform dependent initialization data for Torrent PHY used in TI's J721E SoC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Copyright © 1990 – 2022 jet tsang zeon-git.
All Rights Reverse Engineered.