From 7ec9f34a03e4a08469cca206ff5324f6b99fdc3f Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Fri, 1 Jan 2016 18:48:40 +0530 Subject: ARC: [dts] Introduce Timer bindings ARC Timers have historically been probed directly. As precursor to start probing Timers thru DT introduce these bindings Note that to keep series bisectable, these bindings are not yet used in code. Cc: Daniel Lezcano Cc: devicetree@vger.kernel.org Acked-by: Rob Herring Signed-off-by: Vineet Gupta --- .../devicetree/bindings/timer/snps,arc-timer.txt | 31 ++++++++++++++++++++++ .../devicetree/bindings/timer/snps,archs-gfrc.txt | 14 ++++++++++ .../devicetree/bindings/timer/snps,archs-rtc.txt | 14 ++++++++++ 3 files changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/snps,arc-timer.txt create mode 100644 Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt create mode 100644 Documentation/devicetree/bindings/timer/snps,archs-rtc.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/snps,arc-timer.txt b/Documentation/devicetree/bindings/timer/snps,arc-timer.txt new file mode 100644 index 000000000000..4ef024630d61 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/snps,arc-timer.txt @@ -0,0 +1,31 @@ +Synopsys ARC Local Timer with Interrupt Capabilities +- Found on all ARC CPUs (ARC700/ARCHS) +- Can be optionally programmed to interrupt on Limit +- Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically + TIMER0 used as clockevent provider (true for all ARC cores) + TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS) + +Required properties: + +- compatible : should be "snps,arc-timer" +- interrupts : single Interrupt going into parent intc + (16 for ARCHS cores, 3 for ARC700 cores) +- clocks : phandle to the source clock + +Optional properties: + +- interrupt-parent : phandle to parent intc + +Example: + + timer0 { + compatible = "snps,arc-timer"; + interrupts = <3>; + interrupt-parent = <&core_intc>; + clocks = <&core_clk>; + }; + + timer1 { + compatible = "snps,arc-timer"; + clocks = <&core_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt new file mode 100644 index 000000000000..b6cd1b3922de --- /dev/null +++ b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt @@ -0,0 +1,14 @@ +Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs +- clocksource provider for SMP SoC + +Required properties: + +- compatible : should be "snps,archs-gfrc" +- clocks : phandle to the source clock + +Example: + + gfrc { + compatible = "snps,archs-gfrc"; + clocks = <&core_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt b/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt new file mode 100644 index 000000000000..47bd7a702f3f --- /dev/null +++ b/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt @@ -0,0 +1,14 @@ +Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs +- clocksource provider for UP SoC + +Required properties: + +- compatible : should be "snps,archs-rtc" +- clocks : phandle to the source clock + +Example: + + rtc { + compatible = "snps,arc-rtc"; + clocks = <&core_clk>; + }; -- cgit v1.2.3 From 37f0e658eeeac720f3d558cf5aaf9edf0705ff23 Mon Sep 17 00:00:00 2001 From: Noam Camus Date: Wed, 29 Apr 2015 15:07:43 +0300 Subject: Documentation: Add EZchip vendor to binding list Add EZchip to vendor prefixes list. EZchip introduce the NPS platform for the ARC architecture. Signed-off-by: Noam Camus Acked-by: Rob Herring Cc: Pawel Moll --- Documentation/devicetree/bindings/arc/eznps.txt | 7 +++++++ Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 2 files changed, 8 insertions(+) create mode 100644 Documentation/devicetree/bindings/arc/eznps.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arc/eznps.txt b/Documentation/devicetree/bindings/arc/eznps.txt new file mode 100644 index 000000000000..1aa50c640678 --- /dev/null +++ b/Documentation/devicetree/bindings/arc/eznps.txt @@ -0,0 +1,7 @@ +EZchip NPS Network Processor Platforms Device Tree Bindings +--------------------------------------------------------------------------- + +Appliance main board with NPS400 ASIC. + +Required root node properties: + - compatible = "ezchip,arc-nps"; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 86740d4a270d..ca85c4f3b713 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -86,6 +86,7 @@ eukrea Eukréa Electromatique everest Everest Semiconductor Co. Ltd. everspin Everspin Technologies, Inc. excito Excito +ezchip EZchip Semiconductor fcs Fairchild Semiconductor firefly Firefly focaltech FocalTech Systems Co.,Ltd -- cgit v1.2.3 From a53224577e317d010f61aa1b1b8b18f2b168a137 Mon Sep 17 00:00:00 2001 From: Noam Camus Date: Sat, 17 Oct 2015 22:37:30 +0300 Subject: clocksource: Add NPS400 timers driver Add internal tick generator which is shared by all cores. Each cluster of cores view it through dedicated address. This is used for SMP system where all CPUs synced by same clock source. Signed-off-by: Noam Camus Cc: Daniel Lezcano Cc: Rob Herring Cc: Thomas Gleixner Cc: John Stultz Acked-by: Vineet Gupta Acked-by: Daniel Lezcano --- .../devicetree/bindings/timer/ezchip,nps400-timer.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt new file mode 100644 index 000000000000..c8c03d700382 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt @@ -0,0 +1,15 @@ +NPS Network Processor + +Required properties: + +- compatible : should be "ezchip,nps400-timer" + +Clocks required for compatible = "ezchip,nps400-timer": +- clocks : Must contain a single entry describing the clock input + +Example: + +timer { + compatible = "ezchip,nps400-timer"; + clocks = <&sysclk>; +}; -- cgit v1.2.3 From 44df427c894a4357e43bb35769baefa7cdf09833 Mon Sep 17 00:00:00 2001 From: Noam Camus Date: Thu, 29 Oct 2015 00:26:22 +0200 Subject: irqchip: add nps Internal and external irqchips Adding EZchip NPS400 support. Internal interrupts are handled by Multi Thread Manager (MTM) Once interrupt is serviced MTM is acked for deactivating the interrupt. External interrupts are handled by MTM as well as at Global Interrupt Controller (GIC) e.g. serial and network devices. Signed-off-by: Noam Camus Acked-by: Marc Zyngier Acked-by: Vineet Gupta Acked-by: Jason Cooper Cc: Thomas Gleixner --- .../bindings/interrupt-controller/ezchip,nps400-ic.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt new file mode 100644 index 000000000000..888b2b9f7064 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt @@ -0,0 +1,17 @@ +EZchip NPS Interrupt Controller + +Required properties: + +- compatible : should be "ezchip,nps400-ic" +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. + + +Example: + +intc: interrupt-controller { + compatible = "ezchip,nps400-ic"; + interrupt-controller; + #interrupt-cells = <1>; +}; -- cgit v1.2.3