From a711d43cbbaa4800a15885c1044348982b6c0c4b Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Mon, 8 Oct 2018 01:37:07 +0100 Subject: MIPS: Correct `mmiowb' barrier for `wbflush' platforms Redefine `mmiowb' in terms of `iobarrier_w' so that it works correctly for MIPS I platforms, which have no SYNC machine instruction and use a call to `wbflush' instead. This doesn't change the semantics for CONFIG_CPU_CAVIUM_OCTEON, because `iobarrier_w' expands to `wmb', which is ultimately the same as the current arrangement. For MIPS I platforms this not only makes any code that would happen to use `mmiowb' build and run, but it actually enforces the ordering required as well, as `iobarrier_w' has it already covered with the use of `wmb'. Signed-off-by: Maciej W. Rozycki Signed-off-by: Paul Burton Patchwork: https://patchwork.linux-mips.org/patch/20863/ Cc: Ralf Baechle --- arch/mips/include/asm/io.h | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 312eeed7c5bd..65d2a4d481fc 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -97,6 +97,9 @@ static inline void set_io_port_base(unsigned long base) #define iobarrier_w() wmb() #define iobarrier_sync() iob() +/* Some callers use this older API instead. */ +#define mmiowb() iobarrier_w() + /* * virt_to_phys - map virtual addresses to physical * @address: address to remap @@ -545,14 +548,6 @@ BUILDSTRING(l, u32) BUILDSTRING(q, u64) #endif - -#ifdef CONFIG_CPU_CAVIUM_OCTEON -#define mmiowb() wmb() -#else -/* Depends on MIPS II instruction set */ -#define mmiowb() asm volatile ("sync" ::: "memory") -#endif - static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) { memset((void __force *) addr, val, count); -- cgit v1.2.3