From de56f781e5483fb3b3527aa280df2434f0cb2ace Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Sat, 16 Mar 2024 06:54:41 +0200 Subject: mips: dts: ralink: mt7621: reorder pci?_phy attributes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reorder the attributes of the PCIe PHY nodes node to match what the DTS style guide recommends. Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index aa06d12acacc..284811f32929 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -583,14 +583,18 @@ pcie0_phy: pcie-phy@1e149000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e149000 0x0700>; - clocks = <&sysc MT7621_CLK_XTAL>; + #phy-cells = <1>; + + clocks = <&sysc MT7621_CLK_XTAL>; }; pcie2_phy: pcie-phy@1e14a000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e14a000 0x0700>; - clocks = <&sysc MT7621_CLK_XTAL>; + #phy-cells = <1>; + + clocks = <&sysc MT7621_CLK_XTAL>; }; }; -- cgit v1.2.3