From abf0c1bc94cb16f9eed331ea98ac151d08adf4fe Mon Sep 17 00:00:00 2001 From: Peter Gsellmann Date: Wed, 13 Oct 2010 16:18:51 +0200 Subject: AT91: add board support for Pcontrol_G20 Board is a carrier board for Stamp9G20, with additional peripherals for a building automation system Signed-off-by: Peter Gsellmann [nicolas.ferre@atmel.com: remove machine_desc.io_pg_offst and .phys_io] Signed-off-by: Nicolas Ferre --- arch/arm/configs/pcontrol_g20_defconfig | 175 +++++++++++++++++ arch/arm/mach-at91/Kconfig | 6 + arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/board-pcontrol-g20.c | 322 ++++++++++++++++++++++++++++++++ 4 files changed, 504 insertions(+) create mode 100644 arch/arm/configs/pcontrol_g20_defconfig create mode 100644 arch/arm/mach-at91/board-pcontrol-g20.c (limited to 'arch') diff --git a/arch/arm/configs/pcontrol_g20_defconfig b/arch/arm/configs/pcontrol_g20_defconfig new file mode 100644 index 000000000000..b42ee62c4d77 --- /dev/null +++ b/arch/arm/configs/pcontrol_g20_defconfig @@ -0,0 +1,175 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_CROSS_COMPILE="/opt/arm-2010q1/bin/arm-none-linux-gnueabi-" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_TREE_PREEMPT_RCU=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_NAMESPACES=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_KALLSYMS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +CONFIG_DEFAULT_DEADLINE=y +CONFIG_ARCH_AT91=y +CONFIG_ARCH_AT91SAM9G20=y +CONFIG_MACH_PCONTROL_G20=y +CONFIG_AT91_PROGRAMMABLE_CLOCKS=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0,115200 mem=128M mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) root=/dev/mmcblk0p1 rootwait rw" +CONFIG_VFP=y +CONFIG_BINFMT_MISC=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_IPV6 is not set +CONFIG_VLAN_8021Q=y +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHRAM=m +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ATMEL=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_ATMEL_TCLIB=y +CONFIG_EEPROM_AT24=m +CONFIG_SCSI=m +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=m +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=m +CONFIG_TUN=m +CONFIG_SMSC_PHY=m +CONFIG_BROADCOM_PHY=m +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_MACB=y +CONFIG_SMSC911X=m +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +CONFIG_PPP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_MPPE=m +CONFIG_INPUT_POLLDEV=y +CONFIG_INPUT_SPARSEKMAP=y +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_MATRIX=m +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +# CONFIG_SERIO is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_SERIAL_MAX3100=m +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_R3964=m +CONFIG_I2C=m +CONFIG_I2C_CHARDEV=m +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_GPIO=m +CONFIG_SPI=y +CONFIG_SPI_ATMEL=m +CONFIG_SPI_SPIDEV=m +CONFIG_GPIO_SYSFS=y +CONFIG_W1=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_SLAVE_DS2431=m +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_AT91SAM9X_WATCHDOG=y +# CONFIG_MFD_SUPPORT is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB=y +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=m +CONFIG_USB_LIBUSUAL=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_GADGET=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_G_HID=m +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_ATMELMCI=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91SAM9=y +CONFIG_AUXDISPLAY=y +CONFIG_UIO=y +CONFIG_UIO_PDRV=y +CONFIG_STAGING=y +# CONFIG_STAGING_EXCLUDE_BUILD is not set +CONFIG_IIO=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V4=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ANSI_CPRNG=y +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_CCITT=y diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index abed4d15a7fd..c015b684b4fe 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -375,6 +375,12 @@ config MACH_STAMP9G20 evaluation board. +config MACH_PCONTROL_G20 + bool "PControl G20 CPU module" + help + Select this if you are using taskit's Stamp9G20 CPU module on this + carrier board, beeing the decentralized unit of a building automation + system; featuring nvram, eth-switch, iso-rs485, display, io endif if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 412b3a471a4b..72b6b1b1722a 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o +obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o # AT91SAM9260/AT91SAM9G20 board-specific support obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c new file mode 100644 index 000000000000..bba5a560e02b --- /dev/null +++ b/arch/arm/mach-at91/board-pcontrol-g20.c @@ -0,0 +1,322 @@ +/* + * Copyright (C) 2010 Christian Glindkamp + * taskit GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* + * copied and adjusted from board-stamp9g20.c + * by Peter Gsellmann + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "sam9_smc.h" +#include "generic.h" + + +static void __init pcontrol_g20_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + at91sam9260_initialize(18432000); + + /* DGBU on ttyS0. (Rx, Tx) only TTL -> JTAG connector X7 17,19 ) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS + | ATMEL_UART_RTS); + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) isolated RS485 X5 */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS + | ATMEL_UART_RTS); + + /* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */ + at91_register_uart(AT91SAM9260_ID_US4, 3, 0); + + /* set serial console to ttyS0 (ie, DBGU) */ + at91_set_serial_console(0); +} + + +static void __init init_irq(void) +{ + at91sam9260_init_interrupts(NULL); +} + + +/* + * NAND flash 512MiB 1,8V 8-bit, sector size 128 KiB + */ +static struct atmel_nand_data __initdata nand_data = { + .ale = 21, + .cle = 22, + .rdy_pin = AT91_PIN_PC13, + .enable_pin = AT91_PIN_PC14, +}; + +/* + * Bus timings; unit = 7.57ns + */ +static struct sam9_smc_config __initdata nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 2, + .ncs_write_setup = 0, + .nwe_setup = 2, + + .ncs_read_pulse = 4, + .nrd_pulse = 4, + .ncs_write_pulse = 4, + .nwe_pulse = 4, + + .read_cycle = 7, + .write_cycle = 7, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE + | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 3, +}; + +static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { { + .ncs_read_setup = 16, + .nrd_setup = 18, + .ncs_write_setup = 16, + .nwe_setup = 18, + + .ncs_read_pulse = 63, + .nrd_pulse = 55, + .ncs_write_pulse = 63, + .nwe_pulse = 55, + + .read_cycle = 127, + .write_cycle = 127, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE + | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_SELECT + | AT91_SMC_DBW_8 | AT91_SMC_PS_4 + | AT91_SMC_TDFMODE, + .tdf_cycles = 3, +}, { + .ncs_read_setup = 0, + .nrd_setup = 0, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 8, + .nrd_pulse = 8, + .ncs_write_pulse = 5, + .nwe_pulse = 4, + + .read_cycle = 8, + .write_cycle = 7, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE + | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_SELECT + | AT91_SMC_DBW_16 | AT91_SMC_PS_8 + | AT91_SMC_TDFMODE, + .tdf_cycles = 1, +} }; + +static void __init add_device_nand(void) +{ + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &nand_smc_config); + at91_add_device_nand(&nand_data); +} + + +static void __init add_device_pcontrol(void) +{ + /* configure chip-select 4 (IO compatible to 8051 X4 ) */ + sam9_smc_configure(4, &pcontrol_smc_config[0]); + /* configure chip-select 7 (FerroRAM 256KiBx16bit MR2A16A D4 ) */ + sam9_smc_configure(7, &pcontrol_smc_config[1]); +} + + +/* + * MCI (SD/MMC) + * det_pin, wp_pin and vcc_pin are not connected + */ +#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) +static struct mci_platform_data __initdata mmc_data = { + .slot[0] = { + .bus_width = 4, + }, +}; +#else +static struct at91_mmc_data __initdata mmc_data = { + .wire4 = 1, +}; +#endif + + +/* + * USB Host port + */ +static struct at91_usbh_data __initdata usbh_data = { + .ports = 2, +}; + + +/* + * USB Device port + */ +static struct at91_udc_data __initdata pcontrol_g20_udc_data = { + .vbus_pin = AT91_PIN_PA22, /* Detect +5V bus voltage */ + .pullup_pin = AT91_PIN_PA4, /* K-state, active low */ +}; + + +/* + * MACB Ethernet device + */ +static struct at91_eth_data __initdata macb_data = { + .phy_irq_pin = AT91_PIN_PA28, + .is_rmii = 1, +}; + + +/* + * I2C devices: eeprom and phy/switch + */ +static struct i2c_board_info __initdata pcontrol_g20_i2c_devices[] = { +{ /* D7 address width=2, 8KiB */ + I2C_BOARD_INFO("24c64", 0x50) +}, { /* D8 address width=1, 1 byte has 32 bits! */ + I2C_BOARD_INFO("lan9303", 0x0a) +}, }; + + +/* + * LEDs + */ +static struct gpio_led pcontrol_g20_leds[] = { + { + .name = "LED1", /* red H5 */ + .gpio = AT91_PIN_PB18, + .active_low = 1, + .default_trigger = "none", /* supervisor */ + }, { + .name = "LED2", /* yellow H7 */ + .gpio = AT91_PIN_PB19, + .active_low = 1, + .default_trigger = "mmc0", /* SD-card activity */ + }, { + .name = "LED3", /* green H2 */ + .gpio = AT91_PIN_PB20, + .active_low = 1, + .default_trigger = "heartbeat", /* blinky */ + }, { + .name = "LED4", /* red H3 */ + .gpio = AT91_PIN_PC6, + .active_low = 1, + .default_trigger = "none", /* connection lost */ + }, { + .name = "LED5", /* yellow H6 */ + .gpio = AT91_PIN_PC7, + .active_low = 1, + .default_trigger = "none", /* unsent data */ + }, { + .name = "LED6", /* green H1 */ + .gpio = AT91_PIN_PC9, + .active_low = 1, + .default_trigger = "none", /* snafu */ + } +}; + + +/* + * SPI devices + */ +static struct spi_board_info pcontrol_g20_spi_devices[] = { + { + .modalias = "spidev", /* HMI port X4 */ + .chip_select = 1, + .max_speed_hz = 50 * 1000 * 1000, + .bus_num = 0, + }, { + .modalias = "spidev", /* piggyback A2 */ + .chip_select = 0, + .max_speed_hz = 50 * 1000 * 1000, + .bus_num = 1, + }, +}; + + +/* + * Dallas 1-Wire DS2431 + */ +static struct w1_gpio_platform_data w1_gpio_pdata = { + .pin = AT91_PIN_PA29, + .is_open_drain = 1, +}; + +static struct platform_device w1_device = { + .name = "w1-gpio", + .id = -1, + .dev.platform_data = &w1_gpio_pdata, +}; + +static void add_wire1(void) +{ + at91_set_GPIO_periph(w1_gpio_pdata.pin, 1); + at91_set_multi_drive(w1_gpio_pdata.pin, 1); + platform_device_register(&w1_device); +} + + +static void __init pcontrol_g20_board_init(void) +{ + at91_add_device_serial(); + add_device_nand(); +#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) + at91_add_device_mci(0, &mmc_data); +#else + at91_add_device_mmc(0, &mmc_data); +#endif + at91_add_device_usbh(&usbh_data); + at91_add_device_eth(&macb_data); + at91_add_device_i2c(pcontrol_g20_i2c_devices, + ARRAY_SIZE(pcontrol_g20_i2c_devices)); + add_wire1(); + add_device_pcontrol(); + at91_add_device_spi(pcontrol_g20_spi_devices, + ARRAY_SIZE(pcontrol_g20_spi_devices)); + at91_add_device_udc(&pcontrol_g20_udc_data); + at91_gpio_leds(pcontrol_g20_leds, + ARRAY_SIZE(pcontrol_g20_leds)); + /* piggyback A2 */ + at91_set_gpio_output(AT91_PIN_PB31, 1); +} + + +MACHINE_START(PCONTROL_G20, "PControl G20") + /* Maintainer: pgsellmann@portner-elektronik.at */ + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91sam926x_timer, + .map_io = pcontrol_g20_map_io, + .init_irq = init_irq, + .init_machine = pcontrol_g20_board_init, +MACHINE_END -- cgit v1.2.3 From 184c82e853704ee98e729af0f36a8539355c0e2e Mon Sep 17 00:00:00 2001 From: Peter Horton Date: Fri, 28 May 2010 16:37:26 +0100 Subject: AT91: Fix AT91SAM9G20 reset as per the errata in the data sheet If the SDRAM is not cleanly shutdown before reset it can be left driving the bus, which then stops the bootloader booting from NAND. Signed-off-by: Peter Horton [nicolas.ferre@atmel.com: change file header line order] Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/Makefile | 2 +- arch/arm/mach-at91/at91sam9260.c | 8 ++++- arch/arm/mach-at91/at91sam9g20_reset.S | 55 ++++++++++++++++++++++++++++++++++ 3 files changed, 63 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-at91/at91sam9g20_reset.S (limited to 'arch') diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 72b6b1b1722a..6e97edd47c5f 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_d obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9g20_reset.o obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT572D940HF) += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 0894f1077be7..f8844506eabb 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -25,6 +25,8 @@ #include "generic.h" #include "clock.h" +extern void at91sam9g20_reset(void); + static struct map_desc at91sam9260_io_desc[] __initdata = { { .virtual = AT91_VA_BASE_SYS, @@ -327,7 +329,11 @@ void __init at91sam9260_initialize(unsigned long main_clock) else iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc)); - at91_arch_reset = at91sam9260_reset; + if (cpu_is_at91sam9g20()) + at91_arch_reset = at91sam9g20_reset; + else + at91_arch_reset = at91sam9260_reset; + pm_power_off = at91sam9260_poweroff; at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) | (1 << AT91SAM9260_ID_IRQ2); diff --git a/arch/arm/mach-at91/at91sam9g20_reset.S b/arch/arm/mach-at91/at91sam9g20_reset.S new file mode 100644 index 000000000000..f6e9b037f73c --- /dev/null +++ b/arch/arm/mach-at91/at91sam9g20_reset.S @@ -0,0 +1,55 @@ +/* + * reset AT91SAM9G20 as per errata + * + * (C) BitBox Ltd 2010 + * + * unless the SDRAM is cleanly shutdown before we hit the + * reset register it can be left driving the data bus and + * killing the chance of a subsequent boot from NAND + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#define CP15_CR_I (1 << 12) + +#define SYS_VIRT_OFS (-0x01000000) + +#define SDRAMC_BASE (SYS_VIRT_OFS + 0xffffea00) +#define SDRAMC_TR 0x0004 +#define SDRAMC_LPR 0x0010 +#define SDRAMC_LPCB_POWER_DOWN 2 + +#define RSTC_BASE (SYS_VIRT_OFS + 0xfffffd00) +#define RSTC_CR 0x0000 +#define RSTC_PROCRST (1 << 0) +#define RSTC_PERRST (1 << 2) +#define RSTC_KEY (0xa5 << 24) + + .arm + + .globl at91sam9g20_reset + +at91sam9g20_reset: mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ flush I-cache + + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #CP15_CR_I + mcr p15, 0, r0, c1, c0, 0 @ enable I-cache + + ldr r0, =SDRAMC_BASE @ preload constants + ldr r1, =RSTC_BASE + + mov r2, #1 + mov r3, #SDRAMC_LPCB_POWER_DOWN + ldr r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST + + .balign 32 @ align to cache line + + str r2, [r0, #SDRAMC_TR] @ disable SDRAM access + str r3, [r0, #SDRAMC_LPR] @ power down SDRAM + str r4, [r1, #RSTC_CR] @ reset processor + + b . -- cgit v1.2.3 From ef4d63e6f51d9669e247c47b670a83511b98eb68 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 14 Oct 2010 16:51:36 +0200 Subject: AT91: trivial: align comment of at91sam9g20_reset with one more tab Preparing next patch with longer names Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/at91sam9g20_reset.S | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-at91/at91sam9g20_reset.S b/arch/arm/mach-at91/at91sam9g20_reset.S index f6e9b037f73c..1631c38bc6b8 100644 --- a/arch/arm/mach-at91/at91sam9g20_reset.S +++ b/arch/arm/mach-at91/at91sam9g20_reset.S @@ -33,23 +33,23 @@ .globl at91sam9g20_reset at91sam9g20_reset: mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ flush I-cache + mcr p15, 0, r0, c7, c5, 0 @ flush I-cache mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #CP15_CR_I - mcr p15, 0, r0, c1, c0, 0 @ enable I-cache + mcr p15, 0, r0, c1, c0, 0 @ enable I-cache - ldr r0, =SDRAMC_BASE @ preload constants + ldr r0, =SDRAMC_BASE @ preload constants ldr r1, =RSTC_BASE mov r2, #1 mov r3, #SDRAMC_LPCB_POWER_DOWN ldr r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST - .balign 32 @ align to cache line + .balign 32 @ align to cache line - str r2, [r0, #SDRAMC_TR] @ disable SDRAM access - str r3, [r0, #SDRAMC_LPR] @ power down SDRAM - str r4, [r1, #RSTC_CR] @ reset processor + str r2, [r0, #SDRAMC_TR] @ disable SDRAM access + str r3, [r0, #SDRAMC_LPR] @ power down SDRAM + str r4, [r1, #RSTC_CR] @ reset processor b . -- cgit v1.2.3 From 1345562b449e95e2098cc60eb0eed6d2415cd0b0 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 14 Oct 2010 17:19:11 +0200 Subject: AT91: reset routine cleanup, remove not needed icache flush Generalize assembler reset routine to allow use on several at91sam9 chips. This patch replace double definitions of SDRAM controller registers and RSTC registers with use of classical header files. For this rework, we remove the not needed icache flush as it is already done in the calling function: arm_machine_restart(). Rename at91sam9g20_reset.S to generalize to several chips. Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/Makefile | 2 +- arch/arm/mach-at91/at91sam9260.c | 4 +-- arch/arm/mach-at91/at91sam9_alt_reset.S | 48 ++++++++++++++++++++++++++++ arch/arm/mach-at91/at91sam9g20_reset.S | 55 --------------------------------- 4 files changed, 51 insertions(+), 58 deletions(-) create mode 100644 arch/arm/mach-at91/at91sam9_alt_reset.S delete mode 100644 arch/arm/mach-at91/at91sam9g20_reset.S (limited to 'arch') diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 6e97edd47c5f..c94485227b09 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_d obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9g20_reset.o +obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT572D940HF) += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index f8844506eabb..dfd3529cd101 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -25,7 +25,7 @@ #include "generic.h" #include "clock.h" -extern void at91sam9g20_reset(void); +extern void at91sam9_alt_reset(void); static struct map_desc at91sam9260_io_desc[] __initdata = { { @@ -330,7 +330,7 @@ void __init at91sam9260_initialize(unsigned long main_clock) iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc)); if (cpu_is_at91sam9g20()) - at91_arch_reset = at91sam9g20_reset; + at91_arch_reset = at91sam9_alt_reset; else at91_arch_reset = at91sam9260_reset; diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S new file mode 100644 index 000000000000..e0256deb91fb --- /dev/null +++ b/arch/arm/mach-at91/at91sam9_alt_reset.S @@ -0,0 +1,48 @@ +/* + * reset AT91SAM9G20 as per errata + * + * (C) BitBox Ltd 2010 + * + * unless the SDRAM is cleanly shutdown before we hit the + * reset register it can be left driving the data bus and + * killing the chance of a subsequent boot from NAND + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include + + .arm + + .globl at91sam9_alt_reset + +at91sam9_alt_reset: mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #CR_I + mcr p15, 0, r0, c1, c0, 0 @ enable I-cache + + ldr r0, .at91_va_base_sdramc @ preload constants + ldr r1, .at91_va_base_rstc_cr + + mov r2, #1 + mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN + ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST + + .balign 32 @ align to cache line + + str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access + str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM + str r4, [r1] @ reset processor + + b . + +.at91_va_base_sdramc: + .word AT91_VA_BASE_SYS + AT91_SDRAMC0 +.at91_va_base_rstc_cr: + .word AT91_VA_BASE_SYS + AT91_RSTC_CR diff --git a/arch/arm/mach-at91/at91sam9g20_reset.S b/arch/arm/mach-at91/at91sam9g20_reset.S deleted file mode 100644 index 1631c38bc6b8..000000000000 --- a/arch/arm/mach-at91/at91sam9g20_reset.S +++ /dev/null @@ -1,55 +0,0 @@ -/* - * reset AT91SAM9G20 as per errata - * - * (C) BitBox Ltd 2010 - * - * unless the SDRAM is cleanly shutdown before we hit the - * reset register it can be left driving the data bus and - * killing the chance of a subsequent boot from NAND - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#define CP15_CR_I (1 << 12) - -#define SYS_VIRT_OFS (-0x01000000) - -#define SDRAMC_BASE (SYS_VIRT_OFS + 0xffffea00) -#define SDRAMC_TR 0x0004 -#define SDRAMC_LPR 0x0010 -#define SDRAMC_LPCB_POWER_DOWN 2 - -#define RSTC_BASE (SYS_VIRT_OFS + 0xfffffd00) -#define RSTC_CR 0x0000 -#define RSTC_PROCRST (1 << 0) -#define RSTC_PERRST (1 << 2) -#define RSTC_KEY (0xa5 << 24) - - .arm - - .globl at91sam9g20_reset - -at91sam9g20_reset: mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ flush I-cache - - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #CP15_CR_I - mcr p15, 0, r0, c1, c0, 0 @ enable I-cache - - ldr r0, =SDRAMC_BASE @ preload constants - ldr r1, =RSTC_BASE - - mov r2, #1 - mov r3, #SDRAMC_LPCB_POWER_DOWN - ldr r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST - - .balign 32 @ align to cache line - - str r2, [r0, #SDRAMC_TR] @ disable SDRAM access - str r3, [r0, #SDRAMC_LPR] @ power down SDRAM - str r4, [r1, #RSTC_CR] @ reset processor - - b . -- cgit v1.2.3 From bb413db591d53c29292868577068fa822b84da82 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 14 Oct 2010 19:14:00 +0200 Subject: AT91: reset: extend alternate reset procedure to several chips Several at91sam9 chips need the alternate reset procedure to be sure to halt SDRAM smoothly before resetting the chip. This is an extension of previous patch "Fix AT91SAM9G20 reset" to all chips affected. Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/Makefile | 10 +++++----- arch/arm/mach-at91/at91sam9260.c | 13 +------------ arch/arm/mach-at91/at91sam9261.c | 7 +------ arch/arm/mach-at91/at91sam9263.c | 7 +------ arch/arm/mach-at91/at91sam9rl.c | 7 +------ arch/arm/mach-at91/generic.h | 3 +++ 6 files changed, 12 insertions(+), 35 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index c94485227b09..821eb842795f 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -11,11 +11,11 @@ obj-$(CONFIG_AT91_PMC_UNIT) += clock.o # CPU-specific support obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o -obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o +obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o +obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o +obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o at91sam9_alt_reset.o +obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o at91sam9_alt_reset.o obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index dfd3529cd101..195208b30024 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -25,8 +25,6 @@ #include "generic.h" #include "clock.h" -extern void at91sam9_alt_reset(void); - static struct map_desc at91sam9260_io_desc[] __initdata = { { .virtual = AT91_VA_BASE_SYS, @@ -281,11 +279,6 @@ static struct at91_gpio_bank at91sam9260_gpio[] = { } }; -static void at91sam9260_reset(void) -{ - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); -} - static void at91sam9260_poweroff(void) { at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); @@ -329,11 +322,7 @@ void __init at91sam9260_initialize(unsigned long main_clock) else iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc)); - if (cpu_is_at91sam9g20()) - at91_arch_reset = at91sam9_alt_reset; - else - at91_arch_reset = at91sam9260_reset; - + at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9260_poweroff; at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) | (1 << AT91SAM9260_ID_IRQ2); diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 4ecf37996c77..fcad88668504 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c @@ -257,11 +257,6 @@ static struct at91_gpio_bank at91sam9261_gpio[] = { } }; -static void at91sam9261_reset(void) -{ - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); -} - static void at91sam9261_poweroff(void) { at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); @@ -283,7 +278,7 @@ void __init at91sam9261_initialize(unsigned long main_clock) iotable_init(at91sam9261_sram_desc, ARRAY_SIZE(at91sam9261_sram_desc)); - at91_arch_reset = at91sam9261_reset; + at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9261_poweroff; at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) | (1 << AT91SAM9261_ID_IRQ2); diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 942792d630d8..249f900954d8 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -269,11 +269,6 @@ static struct at91_gpio_bank at91sam9263_gpio[] = { } }; -static void at91sam9263_reset(void) -{ - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); -} - static void at91sam9263_poweroff(void) { at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); @@ -289,7 +284,7 @@ void __init at91sam9263_initialize(unsigned long main_clock) /* Map peripherals */ iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc)); - at91_arch_reset = at91sam9263_reset; + at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9263_poweroff; at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1); diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index 211c5c14a1e6..6a9d24e5ed8e 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c @@ -242,11 +242,6 @@ static struct at91_gpio_bank at91sam9rl_gpio[] = { } }; -static void at91sam9rl_reset(void) -{ - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); -} - static void at91sam9rl_poweroff(void) { at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); @@ -281,7 +276,7 @@ void __init at91sam9rl_initialize(unsigned long main_clock) /* Map SRAM */ iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc)); - at91_arch_reset = at91sam9rl_reset; + at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9rl_poweroff; at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 65c3dc5ba0d0..0c66deb2db39 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -46,6 +46,9 @@ extern void __init at91_clock_associate(const char *id, struct device *dev, cons extern void at91_irq_suspend(void); extern void at91_irq_resume(void); +/* reset */ +extern void at91sam9_alt_reset(void); + /* GPIO */ #define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */ #define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ -- cgit v1.2.3 From 8aeeda822fbfe7da2d4ea391a9757e9532796598 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 22 Oct 2010 17:53:39 +0200 Subject: AT91: pm: use plain cpu_do_idle() for "wait for interrupt" For power management at91_pm_enter() routine, use the cpu_do_idle() for a rock solid "wait for interrupt" implementation. For AT91SAM9 ARM 926 based chips, we can exceed the cache line length as we can access RAM even while in self-refresh mode. We keep plain access to CP15 for at91rm9200 as this feature is not available: instructions have to be in a single cache line. Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/pm.c | 6 ++++-- arch/arm/mach-at91/pm.h | 4 ++++ 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 615668986480..87a31baf1cb3 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -258,16 +258,18 @@ static int at91_pm_enter(suspend_state_t state) * NOTE: the Wait-for-Interrupt instruction needs to be * in icache so no SDRAM accesses are needed until the * wakeup IRQ occurs and self-refresh is terminated. + * For ARM 926 based chips, this requirement is weaker + * as at91sam9 can access a RAM in self-refresh mode. */ asm("b 1f; .align 5; 1:"); asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */ saved_lpr = sdram_selfrefresh_enable(); - asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */ + wait_for_interrupt_enable(); sdram_selfrefresh_disable(saved_lpr); break; case PM_SUSPEND_ON: - asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */ + cpu_do_idle(); break; default: diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 8c87d0c1b8f8..2c4424bfa6c4 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -21,6 +21,7 @@ static inline u32 sdram_selfrefresh_enable(void) } #define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) +#define wait_for_interrupt_enable() asm("mcr p15, 0, r0, c7, c0, 4") #elif defined(CONFIG_ARCH_AT91CAP9) #include @@ -38,6 +39,7 @@ static inline u32 sdram_selfrefresh_enable(void) } #define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr) +#define wait_for_interrupt_enable() cpu_do_idle() #elif defined(CONFIG_ARCH_AT91SAM9G45) #include @@ -74,6 +76,7 @@ static inline u32 sdram_selfrefresh_enable(void) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \ at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \ } while (0) +#define wait_for_interrupt_enable() cpu_do_idle() #else #include @@ -98,5 +101,6 @@ static inline u32 sdram_selfrefresh_enable(void) } #define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr) +#define wait_for_interrupt_enable() cpu_do_idle() #endif -- cgit v1.2.3 From a2a571b74a3881963d8d09deb272d13afe5b49e3 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 22 Oct 2010 18:55:39 +0200 Subject: AT91: pm: make sure that r0 is 0 when dealing with cache operations When using CP15 cache operations (c7), we make sure that Rd (r0) is actually 0 as ARM 926 TRM is saying. Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/pm.c | 9 +++++++-- arch/arm/mach-at91/pm.h | 3 ++- arch/arm/mach-at91/pm_slowclock.S | 1 + 3 files changed, 10 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 87a31baf1cb3..dafbacc25eb1 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -261,8 +261,13 @@ static int at91_pm_enter(suspend_state_t state) * For ARM 926 based chips, this requirement is weaker * as at91sam9 can access a RAM in self-refresh mode. */ - asm("b 1f; .align 5; 1:"); - asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */ + asm volatile ( "mov r0, #0\n\t" + "b 1f\n\t" + ".align 5\n\t" + "1: mcr p15, 0, r0, c7, c10, 4\n\t" + : /* no output */ + : /* no input */ + : "r0"); saved_lpr = sdram_selfrefresh_enable(); wait_for_interrupt_enable(); sdram_selfrefresh_disable(saved_lpr); diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 2c4424bfa6c4..ce9a20699111 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -21,7 +21,8 @@ static inline u32 sdram_selfrefresh_enable(void) } #define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) -#define wait_for_interrupt_enable() asm("mcr p15, 0, r0, c7, c0, 4") +#define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \ + : : "r" (0)) #elif defined(CONFIG_ARCH_AT91CAP9) #include diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S index b6b00a1f6125..f7922a436172 100644 --- a/arch/arm/mach-at91/pm_slowclock.S +++ b/arch/arm/mach-at91/pm_slowclock.S @@ -124,6 +124,7 @@ ENTRY(at91_slow_clock) ldr r5, .at91_va_base_ramc1 /* Drain write buffer */ + mov r0, #0 mcr p15, 0, r0, c7, c10, 4 #ifdef CONFIG_ARCH_AT91RM9200 -- cgit v1.2.3 From 75305d768d296a07fd02df9af3e5de326df1c72e Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 22 Oct 2010 18:27:48 +0200 Subject: at91/atmel-mci: inclusion of sd/mmc driver in at91sam9g45 chip and board This adds the support of atmel-mci sd/mmc driver in at91sam9g45 devices and board files. This also configures the DMA controller slave interface for at_hdmac dmaengine driver. Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/at91sam9g45_devices.c | 165 +++++++++++++++++++++++++++++++ arch/arm/mach-at91/board-sam9m10g45ek.c | 24 +++++ 2 files changed, 189 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index 1276babf84d5..1e8f275c17f6 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include