From 868695e43b94c7ea08155fee29d57b414b7ab060 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 24 Nov 2022 19:16:39 +0000 Subject: clk: renesas: r9a09g011: Add PWM clock and reset entries Add PWM{8..14} clock and reset entries to CPG driver. The PWM IP on the RZ/V2M comes with 16 channels, but the ISP has full control of channels 0 to 7, and channel 15, therefore Linux is only allowed to use channels 8 to 14. The PWM channel 15 shares apb clock and reset with PWM{8..14}. The reset is deasserted by the bootloader/ISP. Add PWM{8..14} clocks to CPG driver and mark apb clock as critical clock, so that the apb clock will be always on. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20221124191643.3193423-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g011-cpg.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index fbef1b35d254..456f02dace60 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -136,6 +136,14 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12), DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12), DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13), + DEF_MOD("cperi_grpf", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, 0x434, 0), + DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, 0x434, 4), + DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, 0x434, 5), + DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, 0x434, 6), + DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, 0x434, 7), + DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8), + DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9), + DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10), DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4), DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5), DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0), @@ -145,6 +153,7 @@ static const struct rzg2l_reset r9a09g011_resets[] = { DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2), DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11), DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13), + DEF_RST_MON(R9A09G011_PWM_GPF_PRESETN, 0x614, 5, 23), DEF_RST(R9A09G011_IIC_GPA_PRESETN, 0x614, 8), DEF_RST(R9A09G011_IIC_GPB_PRESETN, 0x614, 9), DEF_RST_MON(R9A09G011_WDT0_PRESETN, 0x614, 12, 19), @@ -152,6 +161,7 @@ static const struct rzg2l_reset r9a09g011_resets[] = { static const unsigned int r9a09g011_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A09G011_CA53_CLK, + MOD_CLK_BASE + R9A09G011_CPERI_GRPF_PCLK, MOD_CLK_BASE + R9A09G011_GIC_CLK, MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK, MOD_CLK_BASE + R9A09G011_URT_PCLK, -- cgit v1.2.3 From cf919770d05a9b7d10b1609d0b66bc5db8e78a3e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 29 Nov 2022 17:53:25 +0100 Subject: clk: renesas: r8a779g0: Fix OSC predividers According to the table in Note 5 for the OSC clock in Table 8.1.4e ("Lists of CPG clocks generated from PLL5") of the R-Car V4H Series Hardware User's Manual Rev. 0.54, the predividers for the OSC clock are 16 resp. 32 when using a 16.66 resp. 33.33 MHz external crystal. Fixes: 0ab55cf1834177a2 ("clk: renesas: cpg-mssr: Add support for R-Car V4H") Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/dcd572acc584c237f70d2309e038f25040236a87.1669740722.git.geert+renesas@glider.be --- drivers/clk/renesas/r8a779g0-cpg-mssr.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index c6337a408e5e..ec834eb39ffc 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -211,20 +211,20 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC * 14 13 (MHz) * ------------------------------------------------------------------------ - * 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /15 + * 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16 * 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19 * 1 0 Prohibited setting - * 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /38 + * 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32 */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ (((md) & BIT(13)) >> 13)) static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ - { 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 15, }, + { 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 16, }, { 1, 160, 1, 170, 1, 160, 1, 120, 1, 160, 1, 140, 1, 19, }, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, - { 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 38, }, + { 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 32, }, }; static int __init r8a779g0_cpg_mssr_init(struct device *dev) -- cgit v1.2.3 From 121d5713afeaf388bf996e20233142bd289b5f68 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 29 Nov 2022 17:54:58 +0100 Subject: clk: renesas: rcar-gen4: Restore PLL enum sort order When CLK_TYPE_GEN4_PLL4 was added to the rcar_gen4_clk_types enum, it was inserted at a random location. Restore sort order of the clock types referring to PLLs. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/dbd61ed19f79e9ae751fbb533d6c946e810e4359.1669740824.git.geert+renesas@glider.be --- drivers/clk/renesas/rcar-gen4-cpg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h index 0b15dcfdca7b..0a0e3bdb3a66 100644 --- a/drivers/clk/renesas/rcar-gen4-cpg.h +++ b/drivers/clk/renesas/rcar-gen4-cpg.h @@ -15,8 +15,8 @@ enum rcar_gen4_clk_types { CLK_TYPE_GEN4_PLL2, CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */ CLK_TYPE_GEN4_PLL3, - CLK_TYPE_GEN4_PLL5, CLK_TYPE_GEN4_PLL4, + CLK_TYPE_GEN4_PLL5, CLK_TYPE_GEN4_PLL6, CLK_TYPE_GEN4_SDSRC, CLK_TYPE_GEN4_SDH, -- cgit v1.2.3 From ff1dd4a8422beebbc5df98671fcd0ad47c57b7b2 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 1 Dec 2022 11:56:27 +0200 Subject: clk: renesas: r8a779g0: Add display related clocks Add clocks related to display which are needed to get the DSI output working. Extracted from Renesas BSP tree. Signed-off-by: Tomi Valkeinen Reviewed-by: Kieran Bingham Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20221201095631.89448-4-tomi.valkeinen+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779g0-cpg-mssr.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index ec834eb39ffc..745ff9214fe8 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -145,6 +145,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1), DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1), DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1), + DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1), + DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884), DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870), DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870), @@ -161,6 +163,11 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC), DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC), DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC), + DEF_MOD("dis0", 411, R8A779G0_CLK_VIOBUSD2), + DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_VIOBUSD2), + DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_VIOBUSD2), + DEF_MOD("fcpvd0", 508, R8A779G0_CLK_VIOBUSD2), + DEF_MOD("fcpvd1", 509, R8A779G0_CLK_VIOBUSD2), DEF_MOD("hscif0", 514, R8A779G0_CLK_SASYNCPERD1), DEF_MOD("hscif1", 515, R8A779G0_CLK_SASYNCPERD1), DEF_MOD("hscif2", 516, R8A779G0_CLK_SASYNCPERD1), @@ -193,6 +200,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2), DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2), DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4), + DEF_MOD("vspd0", 830, R8A779G0_CLK_VIOBUSD2), + DEF_MOD("vspd1", 831, R8A779G0_CLK_VIOBUSD2), DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R), DEF_MOD("cmt0", 910, R8A779G0_CLK_R), DEF_MOD("cmt1", 911, R8A779G0_CLK_R), -- cgit v1.2.3 From d459f557ad76f449687e76fcb94f1009551dd669 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 5 Dec 2022 14:59:50 +0000 Subject: clk: renesas: r9a09g011: Add TIM clock and reset entries Add Compare-Match Timer (TIM) clock and reset entries to CPG driver. The TIM IP on the RZ/V2M comes with 32 channels, but the ISP has full control of channels 0 to 7, and channels 24 to 31. Therefore Linux is only allowed to use channels 8 to 23. The TIM has shared peripheral clock with other modules, so mark it as critical clock. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20221205145955.391526-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g011-cpg.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index 456f02dace60..6ad428c4102b 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -133,7 +133,25 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9), DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12), DEF_MOD("iic_pclk0", R9A09G011_IIC_PCLK0, CLK_SEL_E, 0x420, 12), + DEF_MOD("cperi_grpb", R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E, 0x424, 0), + DEF_MOD("tim_clk_8", R9A09G011_TIM8_CLK, CLK_MAIN_2, 0x424, 4), + DEF_MOD("tim_clk_9", R9A09G011_TIM9_CLK, CLK_MAIN_2, 0x424, 5), + DEF_MOD("tim_clk_10", R9A09G011_TIM10_CLK, CLK_MAIN_2, 0x424, 6), + DEF_MOD("tim_clk_11", R9A09G011_TIM11_CLK, CLK_MAIN_2, 0x424, 7), + DEF_MOD("tim_clk_12", R9A09G011_TIM12_CLK, CLK_MAIN_2, 0x424, 8), + DEF_MOD("tim_clk_13", R9A09G011_TIM13_CLK, CLK_MAIN_2, 0x424, 9), + DEF_MOD("tim_clk_14", R9A09G011_TIM14_CLK, CLK_MAIN_2, 0x424, 10), + DEF_MOD("tim_clk_15", R9A09G011_TIM15_CLK, CLK_MAIN_2, 0x424, 11), DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12), + DEF_MOD("cperi_grpc", R9A09G011_CPERI_GRPC_PCLK, CLK_SEL_E, 0x428, 0), + DEF_MOD("tim_clk_16", R9A09G011_TIM16_CLK, CLK_MAIN_2, 0x428, 4), + DEF_MOD("tim_clk_17", R9A09G011_TIM17_CLK, CLK_MAIN_2, 0x428, 5), + DEF_MOD("tim_clk_18", R9A09G011_TIM18_CLK, CLK_MAIN_2, 0x428, 6), + DEF_MOD("tim_clk_19", R9A09G011_TIM19_CLK, CLK_MAIN_2, 0x428, 7), + DEF_MOD("tim_clk_20", R9A09G011_TIM20_CLK, CLK_MAIN_2, 0x428, 8), + DEF_MOD("tim_clk_21", R9A09G011_TIM21_CLK, CLK_MAIN_2, 0x428, 9), + DEF_MOD("tim_clk_22", R9A09G011_TIM22_CLK, CLK_MAIN_2, 0x428, 10), + DEF_MOD("tim_clk_23", R9A09G011_TIM23_CLK, CLK_MAIN_2, 0x428, 11), DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12), DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13), DEF_MOD("cperi_grpf", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, 0x434, 0), @@ -153,6 +171,8 @@ static const struct rzg2l_reset r9a09g011_resets[] = { DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2), DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11), DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13), + DEF_RST(R9A09G011_TIM_GPB_PRESETN, 0x614, 1), + DEF_RST(R9A09G011_TIM_GPC_PRESETN, 0x614, 2), DEF_RST_MON(R9A09G011_PWM_GPF_PRESETN, 0x614, 5, 23), DEF_RST(R9A09G011_IIC_GPA_PRESETN, 0x614, 8), DEF_RST(R9A09G011_IIC_GPB_PRESETN, 0x614, 9), @@ -161,6 +181,8 @@ static const struct rzg2l_reset r9a09g011_resets[] = { static const unsigned int r9a09g011_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A09G011_CA53_CLK, + MOD_CLK_BASE + R9A09G011_CPERI_GRPB_PCLK, + MOD_CLK_BASE + R9A09G011_CPERI_GRPC_PCLK, MOD_CLK_BASE + R9A09G011_CPERI_GRPF_PCLK, MOD_CLK_BASE + R9A09G011_GIC_CLK, MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK, -- cgit v1.2.3 From 5edf5b51e760af749c4a8e67cde92db4f3680be5 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 12 Dec 2022 17:27:49 +0000 Subject: clk: renesas: r9a09g011: Add USB clock and reset entries Add USB clock and reset entries to CPG driver. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20221212172804.1277751-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g011-cpg.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index 6ad428c4102b..380f7a158b5a 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -23,10 +23,12 @@ #define DIV_A DDIV_PACK(0x200, 0, 3) #define DIV_B DDIV_PACK(0x204, 0, 2) +#define DIV_D DDIV_PACK(0x204, 4, 2) #define DIV_E DDIV_PACK(0x204, 8, 1) #define DIV_W DDIV_PACK(0x328, 0, 3) #define SEL_B SEL_PLL_PACK(0x214, 0, 1) +#define SEL_D SEL_PLL_PACK(0x214, 1, 1) #define SEL_E SEL_PLL_PACK(0x214, 2, 1) #define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1) @@ -50,10 +52,12 @@ enum clk_ids { CLK_PLL4, CLK_DIV_A, CLK_DIV_B, + CLK_DIV_D, CLK_DIV_E, CLK_DIV_W, CLK_SEL_B, CLK_SEL_B_D2, + CLK_SEL_D, CLK_SEL_E, CLK_SEL_W0, @@ -81,6 +85,13 @@ static const struct clk_div_table dtable_divb[] = { {0, 0}, }; +static const struct clk_div_table dtable_divd[] = { + {0, 1}, + {1, 2}, + {2, 4}, + {0, 0}, +}; + static const struct clk_div_table dtable_divw[] = { {0, 6}, {1, 7}, @@ -94,6 +105,7 @@ static const struct clk_div_table dtable_divw[] = { /* Mux clock tables */ static const char * const sel_b[] = { ".main", ".divb" }; +static const char * const sel_d[] = { ".main", ".divd" }; static const char * const sel_e[] = { ".main", ".dive" }; static const char * const sel_w[] = { ".main", ".divw" }; @@ -115,10 +127,12 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { DEF_DIV_RO(".diva", CLK_DIV_A, CLK_PLL1, DIV_A, dtable_diva), DEF_DIV_RO(".divb", CLK_DIV_B, CLK_PLL2_400, DIV_B, dtable_divb), + DEF_DIV_RO(".divd", CLK_DIV_D, CLK_PLL2_200, DIV_D, dtable_divd), DEF_DIV_RO(".dive", CLK_DIV_E, CLK_PLL2_100, DIV_E, NULL), DEF_DIV_RO(".divw", CLK_DIV_W, CLK_PLL4, DIV_W, dtable_divw), DEF_MUX_RO(".selb", CLK_SEL_B, SEL_B, sel_b), + DEF_MUX_RO(".seld", CLK_SEL_D, SEL_D, sel_d), DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e), DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w), @@ -131,6 +145,9 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8), DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8), DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9), + DEF_MOD("usb_aclk_h", R9A09G011_USB_ACLK_H, CLK_SEL_D, 0x40c, 4), + DEF_MOD("usb_aclk_p", R9A09G011_USB_ACLK_P, CLK_SEL_D, 0x40c, 5), + DEF_MOD("usb_pclk", R9A09G011_USB_PCLK, CLK_SEL_E, 0x40c, 6), DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12), DEF_MOD("iic_pclk0", R9A09G011_IIC_PCLK0, CLK_SEL_E, 0x420, 12), DEF_MOD("cperi_grpb", R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E, 0x424, 0), @@ -169,6 +186,10 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { static const struct rzg2l_reset r9a09g011_resets[] = { DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2), + DEF_RST(R9A09G011_USB_PRESET_N, 0x608, 7), + DEF_RST(R9A09G011_USB_DRD_RESET, 0x608, 8), + DEF_RST(R9A09G011_USB_ARESETN_P, 0x608, 9), + DEF_RST(R9A09G011_USB_ARESETN_H, 0x608, 10), DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11), DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13), DEF_RST(R9A09G011_TIM_GPB_PRESETN, 0x614, 1), -- cgit v1.2.3 From d969103ac89de797fda351aa984f69602b149a72 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 13 Dec 2022 23:01:26 +0000 Subject: clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries Add SDHI/eMMC clock/reset entries to CPG driver. Signed-off-by: Phil Edworthy Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20221213230129.549968-2-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g011-cpg.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index 380f7a158b5a..3d06baf5061d 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -30,6 +30,7 @@ #define SEL_B SEL_PLL_PACK(0x214, 0, 1) #define SEL_D SEL_PLL_PACK(0x214, 1, 1) #define SEL_E SEL_PLL_PACK(0x214, 2, 1) +#define SEL_SDI SEL_PLL_PACK(0x300, 0, 1) #define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1) enum clk_ids { @@ -59,6 +60,7 @@ enum clk_ids { CLK_SEL_B_D2, CLK_SEL_D, CLK_SEL_E, + CLK_SEL_SDI, CLK_SEL_W0, /* Module Clocks */ @@ -92,6 +94,7 @@ static const struct clk_div_table dtable_divd[] = { {0, 0}, }; + static const struct clk_div_table dtable_divw[] = { {0, 6}, {1, 7}, @@ -108,6 +111,7 @@ static const char * const sel_b[] = { ".main", ".divb" }; static const char * const sel_d[] = { ".main", ".divd" }; static const char * const sel_e[] = { ".main", ".dive" }; static const char * const sel_w[] = { ".main", ".divw" }; +static const char * const sel_sdi[] = { ".main", ".pll2_200" }; static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { /* External Clock Inputs */ @@ -134,6 +138,7 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { DEF_MUX_RO(".selb", CLK_SEL_B, SEL_B, sel_b), DEF_MUX_RO(".seld", CLK_SEL_D, SEL_D, sel_d), DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e), + DEF_MUX(".selsdi", CLK_SEL_SDI, SEL_SDI, sel_sdi), DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w), DEF_FIXED(".selb_d2", CLK_SEL_B_D2, CLK_SEL_B, 1, 2), @@ -142,6 +147,18 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2), DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5), + DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0), + DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1), + DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2), + DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3), + DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4), + DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5), + DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6), + DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7), + DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8), + DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9), + DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10), + DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11), DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8), DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8), DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9), @@ -186,6 +203,9 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { static const struct rzg2l_reset r9a09g011_resets[] = { DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2), + DEF_RST_MON(R9A09G011_SDI0_IXRST, 0x608, 0, 6), + DEF_RST_MON(R9A09G011_SDI1_IXRST, 0x608, 1, 7), + DEF_RST_MON(R9A09G011_EMM_IXRST, 0x608, 2, 8), DEF_RST(R9A09G011_USB_PRESET_N, 0x608, 7), DEF_RST(R9A09G011_USB_DRD_RESET, 0x608, 8), DEF_RST(R9A09G011_USB_ARESETN_P, 0x608, 9), -- cgit v1.2.3 From a278d0c92be9d90307114b05c3edb1e7354d8412 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 21 Dec 2022 21:27:03 +0000 Subject: clk: renesas: r9a07g044: Add clock and reset entries for CRU Add CRU clock and reset entries to CPG driver. CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular sequence for the CRU block hence add these clocks to r9a07g044_no_pm_mod_clks[] array and pass it as part of CPG data for both RZ/G2L and RZ/V2L SoCs. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20221221212703.348278-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g044-cpg.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index f5550fccb029..c597414a94d8 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -182,7 +182,7 @@ static const struct { }; static const struct { - struct rzg2l_mod_clk common[75]; + struct rzg2l_mod_clk common[79]; #ifdef CONFIG_CLK_R9A07G054 struct rzg2l_mod_clk drp[0]; #endif @@ -250,6 +250,14 @@ static const struct { 0x558, 1), DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1, 0x558, 2), + DEF_MOD("cru_sysclk", R9A07G044_CRU_SYSCLK, CLK_M2_DIV2, + 0x564, 0), + DEF_MOD("cru_vclk", R9A07G044_CRU_VCLK, R9A07G044_CLK_M2, + 0x564, 1), + DEF_MOD("cru_pclk", R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT, + 0x564, 2), + DEF_MOD("cru_aclk", R9A07G044_CRU_ACLK, R9A07G044_CLK_M0, + 0x564, 3), DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1, 0x568, 0), DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2, @@ -368,6 +376,9 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0), DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1), DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2), + DEF_RST(R9A07G044_CRU_CMN_RSTB, 0x864, 0), + DEF_RST(R9A07G044_CRU_PRESETN, 0x864, 1), + DEF_RST(R9A07G044_CRU_ARESETN, 0x864, 2), DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0), DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1), DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2), @@ -412,6 +423,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A07G044_DMAC_ACLK, }; +static const unsigned int r9a07g044_no_pm_mod_clks[] = { + MOD_CLK_BASE + R9A07G044_CRU_SYSCLK, + MOD_CLK_BASE + R9A07G044_CRU_VCLK, +}; + #ifdef CONFIG_CLK_R9A07G044 const struct rzg2l_cpg_info r9a07g044_cpg_info = { /* Core Clocks */ @@ -429,6 +445,10 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = { .num_mod_clks = ARRAY_SIZE(mod_clks.common), .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1, + /* No PM Module Clocks */ + .no_pm_mod_clks = r9a07g044_no_pm_mod_clks, + .num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks), + /* Resets */ .resets = r9a07g044_resets, .num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */ @@ -454,6 +474,10 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = { .num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp), .num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1, + /* No PM Module Clocks */ + .no_pm_mod_clks = r9a07g044_no_pm_mod_clks, + .num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks), + /* Resets */ .resets = r9a07g044_resets, .num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */ -- cgit v1.2.3 From fbfd614aeaa2853c2c575299dfe2458db8eff67e Mon Sep 17 00:00:00 2001 From: Alexey Khoroshilov Date: Fri, 23 Dec 2022 17:40:17 +0300 Subject: clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failed If cpg_mssr_common_init() fails after assigning priv to global variable cpg_mssr_priv, it deallocates priv, but cpg_mssr_priv keeps dangling pointer that potentially can be used later. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 1f7db7bbf031 ("clk: renesas: cpg-mssr: Add early clock support") Signed-off-by: Alexey Khoroshilov Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/1671806417-32623-1-git-send-email-khoroshilov@ispras.ru Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/renesas-cpg-mssr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 1a0cdf001b2f..5dce9779324d 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -989,7 +989,6 @@ static int __init cpg_mssr_common_init(struct device *dev, goto out_err; } - cpg_mssr_priv = priv; priv->num_core_clks = info->num_total_core_clks; priv->num_mod_clks = info->num_hw_mod_clks; priv->last_dt_core_clk = info->last_dt_core_clk; @@ -1019,6 +1018,8 @@ static int __init cpg_mssr_common_init(struct device *dev, if (error) goto out_err; + cpg_mssr_priv = priv; + return 0; out_err: -- cgit v1.2.3 From 1fd62f262ee7921a5600d77a1b92614542cca686 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 25 Dec 2022 22:26:29 +0100 Subject: clk: meson: mpll: Switch from .round_rate to .determine_rate clk_ops.round_rate will be removed at some point. It's replacement is .determine_rate. Switch clk-mpll over to use .determine_rate. Signed-off-by: Martin Blumenstingl Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20221225212632.2760126-2-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet --- drivers/clk/meson/clk-mpll.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c index fc9df4860872..20255e129b37 100644 --- a/drivers/clk/meson/clk-mpll.c +++ b/drivers/clk/meson/clk-mpll.c @@ -87,16 +87,22 @@ static unsigned long mpll_recalc_rate(struct clk_hw *hw, return rate < 0 ? 0 : rate; } -static long mpll_round_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long *parent_rate) +static int mpll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); unsigned int sdm, n2; + long rate; + + params_from_rate(req->rate, req->best_parent_rate, &sdm, &n2, + mpll->flags); - params_from_rate(rate, *parent_rate, &sdm, &n2, mpll->flags); - return rate_from_params(*parent_rate, sdm, n2); + rate = rate_from_params(req->best_parent_rate, sdm, n2); + if (rate < 0) + return rate; + + req->rate = rate; + return 0; } static int mpll_set_rate(struct clk_hw *hw, @@ -157,13 +163,13 @@ static int mpll_init(struct clk_hw *hw) const struct clk_ops meson_clk_mpll_ro_ops = { .recalc_rate = mpll_recalc_rate, - .round_rate = mpll_round_rate, + .determine_rate = mpll_determine_rate, }; EXPORT_SYMBOL_GPL(meson_clk_mpll_ro_ops); const struct clk_ops meson_clk_mpll_ops = { .recalc_rate = mpll_recalc_rate, - .round_rate = mpll_round_rate, + .determine_rate = mpll_determine_rate, .set_rate = mpll_set_rate, .init = mpll_init, }; -- cgit v1.2.3 From 581f772566efea8a3fe6a166fe0b88febdba1b26 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 25 Dec 2022 22:26:30 +0100 Subject: clk: meson: dualdiv: switch from .round_rate to .determine_rate clk_ops.round_rate will be removed at some point. It's replacement is .determine_rate. Switch clk-dualdiv over to use .determine_rate. Signed-off-by: Martin Blumenstingl Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20221225212632.2760126-3-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet --- drivers/clk/meson/clk-dualdiv.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/meson/clk-dualdiv.c b/drivers/clk/meson/clk-dualdiv.c index c5ca23a5e3e8..feae49a8f6dc 100644 --- a/drivers/clk/meson/clk-dualdiv.c +++ b/drivers/clk/meson/clk-dualdiv.c @@ -86,18 +86,23 @@ __dualdiv_get_setting(unsigned long rate, unsigned long parent_rate, return (struct meson_clk_dualdiv_param *)&table[best_i]; } -static long meson_clk_dualdiv_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int meson_clk_dualdiv_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_dualdiv_data *dualdiv = meson_clk_dualdiv_data(clk); - const struct meson_clk_dualdiv_param *setting = - __dualdiv_get_setting(rate, *parent_rate, dualdiv); + const struct meson_clk_dualdiv_param *setting; - if (!setting) - return meson_clk_dualdiv_recalc_rate(hw, *parent_rate); + setting = __dualdiv_get_setting(req->rate, req->best_parent_rate, + dualdiv); + if (setting) + req->rate = __dualdiv_param_to_rate(req->best_parent_rate, + setting); + else + req->rate = meson_clk_dualdiv_recalc_rate(hw, + req->best_parent_rate); - return __dualdiv_param_to_rate(*parent_rate, setting); + return 0; } static int meson_clk_dualdiv_set_rate(struct clk_hw *hw, unsigned long rate, @@ -122,7 +127,7 @@ static int meson_clk_dualdiv_set_rate(struct clk_hw *hw, unsigned long rate, const struct clk_ops meson_clk_dualdiv_ops = { .recalc_rate = meson_clk_dualdiv_recalc_rate, - .round_rate = meson_clk_dualdiv_round_rate, + .determine_rate = meson_clk_dualdiv_determine_rate, .set_rate = meson_clk_dualdiv_set_rate, }; EXPORT_SYMBOL_GPL(meson_clk_dualdiv_ops); -- cgit v1.2.3 From 9ac323943f7a4c5e5b7c5d4bd6c8225f62b94c43 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 25 Dec 2022 22:26:31 +0100 Subject: clk: meson: sclk-div: switch from .round_rate to .determine_rate clk_ops.round_rate will be removed at some point. It's replacement is .determine_rate. Switch sclk-div over to use .determine_rate. Signed-off-by: Martin Blumenstingl Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20221225212632.2760126-4-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet --- drivers/clk/meson/sclk-div.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/meson/sclk-div.c b/drivers/clk/meson/sclk-div.c index 76d31c0a3342..d12c45c4c261 100644 --- a/drivers/clk/meson/sclk-div.c +++ b/drivers/clk/meson/sclk-div.c @@ -96,16 +96,17 @@ static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate, return bestdiv; } -static long sclk_div_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int sclk_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_regmap *clk = to_clk_regmap(hw); struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); int div; - div = sclk_div_bestdiv(hw, rate, prate, sclk); + div = sclk_div_bestdiv(hw, req->rate, &req->best_parent_rate, sclk); + req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); - return DIV_ROUND_UP_ULL((u64)*prate, div); + return 0; } static void sclk_apply_ratio(struct clk_regmap *clk, @@ -237,7 +238,7 @@ static int sclk_div_init(struct clk_hw *hw) const struct clk_ops meson_sclk_div_ops = { .recalc_rate = sclk_div_recalc_rate, - .round_rate = sclk_div_round_rate, + .determine_rate = sclk_div_determine_rate, .set_rate = sclk_div_set_rate, .enable = sclk_div_enable, .disable = sclk_div_disable, -- cgit v1.2.3 From 716592fdb5e255a1b9dcb444822c9c1f9a1e248c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 25 Dec 2022 22:26:32 +0100 Subject: clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate clk_ops.round_rate will be removed at some point. It's replacement is .determine_rate. Switch clk-cpu-dyndiv over to use .determine_rate. Signed-off-by: Martin Blumenstingl Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20221225212632.2760126-5-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet --- drivers/clk/meson/clk-cpu-dyndiv.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/meson/clk-cpu-dyndiv.c b/drivers/clk/meson/clk-cpu-dyndiv.c index 36976927fe82..8778c149d26a 100644 --- a/drivers/clk/meson/clk-cpu-dyndiv.c +++ b/drivers/clk/meson/clk-cpu-dyndiv.c @@ -27,14 +27,13 @@ static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw, NULL, 0, data->div.width); } -static long meson_clk_cpu_dyndiv_round_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long *prate) +static int meson_clk_cpu_dyndiv_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk); - return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0); + return divider_determine_rate(hw, req, NULL, data->div.width, 0); } static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate, @@ -63,7 +62,7 @@ static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate, const struct clk_ops meson_clk_cpu_dyndiv_ops = { .recalc_rate = meson_clk_cpu_dyndiv_recalc_rate, - .round_rate = meson_clk_cpu_dyndiv_round_rate, + .determine_rate = meson_clk_cpu_dyndiv_determine_rate, .set_rate = meson_clk_cpu_dyndiv_set_rate, }; EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops); -- cgit v1.2.3 From 3ed741db04f58e8df0d46cec7ecfc4bfd075f047 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sat, 14 Jan 2023 15:34:58 -0800 Subject: clk: vc5: Use `clamp()` to restrict PLL range The VCO frequency needs to be within a certain range and the driver enforces this. Make use of the clamp macro to implement this instead of open-coding it. This makes the code a bit shorter and also semanticly stronger. Signed-off-by: Lars-Peter Clausen Link: https://lore.kernel.org/r/20230114233500.3294789-1-lars@metafoo.de Reviewed-by: Luca Ceresoli Signed-off-by: Stephen Boyd --- drivers/clk/clk-versaclock5.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c index e9737969170e..54fee43d6564 100644 --- a/drivers/clk/clk-versaclock5.c +++ b/drivers/clk/clk-versaclock5.c @@ -449,10 +449,7 @@ static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate, u32 div_int; u64 div_frc; - if (rate < VC5_PLL_VCO_MIN) - rate = VC5_PLL_VCO_MIN; - if (rate > VC5_PLL_VCO_MAX) - rate = VC5_PLL_VCO_MAX; + rate = clamp(rate, VC5_PLL_VCO_MIN, VC5_PLL_VCO_MAX); /* Determine integer part, which is 12 bit wide */ div_int = rate / *parent_rate; -- cgit v1.2.3 From 4411da3209298b4ababc7d12940339c664e8db4a Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sat, 14 Jan 2023 15:34:59 -0800 Subject: clk: vc5: Add support for 5P49V60 The 5P49V60 is very similar to the existing supported clock chips of the versaclock5 driver and uses the same register map layout. But its maximum VCO frequency is 2.7 GHz instead of 3 GHz for the other supported devices. Add a vco_max field to the chip info field to allow to specify a per device variant maximum VCO frequency. Signed-off-by: Lars-Peter Clausen Link: https://lore.kernel.org/r/20230114233500.3294789-2-lars@metafoo.de Reviewed-by: Luca Ceresoli Signed-off-by: Stephen Boyd --- drivers/clk/clk-versaclock5.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c index 54fee43d6564..fa71a57875ce 100644 --- a/drivers/clk/clk-versaclock5.c +++ b/drivers/clk/clk-versaclock5.c @@ -122,9 +122,8 @@ #define VC5_GLOBAL_REGISTER 0x76 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5) -/* PLL/VCO runs between 2.5 GHz and 3.0 GHz */ +/* The minimum VCO frequency is 2.5 GHz. The maximum is variant specific. */ #define VC5_PLL_VCO_MIN 2500000000UL -#define VC5_PLL_VCO_MAX 3000000000UL /* VC5 Input mux settings */ #define VC5_MUX_IN_XIN BIT(0) @@ -150,6 +149,7 @@ enum vc5_model { IDT_VC5_5P49V5925, IDT_VC5_5P49V5933, IDT_VC5_5P49V5935, + IDT_VC6_5P49V60, IDT_VC6_5P49V6901, IDT_VC6_5P49V6965, IDT_VC6_5P49V6975, @@ -161,6 +161,7 @@ struct vc5_chip_info { const unsigned int clk_fod_cnt; const unsigned int clk_out_cnt; const u32 flags; + const unsigned long vco_max; }; struct vc5_driver_data; @@ -446,10 +447,11 @@ static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); + struct vc5_driver_data *vc5 = hwdata->vc5; u32 div_int; u64 div_frc; - rate = clamp(rate, VC5_PLL_VCO_MIN, VC5_PLL_VCO_MAX); + rate = clamp(rate, VC5_PLL_VCO_MIN, vc5->chip_info->vco_max); /* Determine integer part, which is 12 bit wide */ div_int = rate / *parent_rate; @@ -1209,6 +1211,7 @@ static const struct vc5_chip_info idt_5p49v5923_info = { .clk_fod_cnt = 2, .clk_out_cnt = 3, .flags = 0, + .vco_max = 3000000000UL, }; static const struct vc5_chip_info idt_5p49v5925_info = { @@ -1216,6 +1219,7 @@ static const struct vc5_chip_info idt_5p49v5925_info = { .clk_fod_cnt = 4, .clk_out_cnt = 5, .flags = 0, + .vco_max = 3000000000UL, }; static const struct vc5_chip_info idt_5p49v5933_info = { @@ -1223,6 +1227,7 @@ static const struct vc5_chip_info idt_5p49v5933_info = { .clk_fod_cnt = 2, .clk_out_cnt = 3, .flags = VC5_HAS_INTERNAL_XTAL, + .vco_max = 3000000000UL, }; static const struct vc5_chip_info idt_5p49v5935_info = { @@ -1230,6 +1235,15 @@ static const struct vc5_chip_info idt_5p49v5935_info = { .clk_fod_cnt = 4, .clk_out_cnt = 5, .flags = VC5_HAS_INTERNAL_XTAL, + .vco_max = 3000000000UL, +}; + +static const struct vc5_chip_info idt_5p49v60_info = { + .model = IDT_VC6_5P49V60, + .clk_fod_cnt = 4, + .clk_out_cnt = 5, + .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT, + .vco_max = 2700000000UL, }; static const struct vc5_chip_info idt_5p49v6901_info = { @@ -1237,6 +1251,7 @@ static const struct vc5_chip_info idt_5p49v6901_info = { .clk_fod_cnt = 4, .clk_out_cnt = 5, .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT, + .vco_max = 3000000000UL, }; static const struct vc5_chip_info idt_5p49v6965_info = { @@ -1244,6 +1259,7 @@ static const struct vc5_chip_info idt_5p49v6965_info = { .clk_fod_cnt = 4, .clk_out_cnt = 5, .flags = VC5_HAS_BYPASS_SYNC_BIT, + .vco_max = 3000000000UL, }; static const struct vc5_chip_info idt_5p49v6975_info = { @@ -1251,6 +1267,7 @@ static const struct vc5_chip_info idt_5p49v6975_info = { .clk_fod_cnt = 4, .clk_out_cnt = 5, .flags = VC5_HAS_BYPASS_SYNC_BIT | VC5_HAS_INTERNAL_XTAL, + .vco_max = 3000000000UL, }; static const struct i2c_device_id vc5_id[] = { @@ -1258,6 +1275,7 @@ static const struct i2c_device_id vc5_id[] = { { "5p49v5925", .driver_data = IDT_VC5_5P49V5925 }, { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 }, { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 }, + { "5p49v60", .driver_data = IDT_VC6_5P49V60 }, { "5p49v6901", .driver_data = IDT_VC6_5P49V6901 }, { "5p49v6965", .driver_data = IDT_VC6_5P49V6965 }, { "5p49v6975", .driver_data = IDT_VC6_5P49V6975 }, @@ -1270,6 +1288,7 @@ static const struct of_device_id clk_vc5_of_match[] = { { .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info }, { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info }, { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info }, + { .compatible = "idt,5p49v60", .data = &idt_5p49v60_info }, { .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info }, { .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info }, { .compatible = "idt,5p49v6975", .data = &idt_5p49v6975_info }, -- cgit v1.2.3 From d4638642aa0a2b39d6f7666538c7df073f67aadb Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Thu, 5 Jan 2023 16:22:54 +0100 Subject: clk: renesas: r9a06g032: Handle h2mode setting based on USBF presence The CFG_USB[H2MODE] allows to switch the USB configuration. The configuration supported are: - One host and one device or - Two hosts Set CFG_USB[H2MODE] based on the USBF controller (USB device) availability. Signed-off-by: Herve Codina Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230105152257.310642-3-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a06g032-clocks.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index 983faa5707b9..087146f2ee06 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -25,6 +25,8 @@ #include #include +#define R9A06G032_SYSCTRL_USB 0x00 +#define R9A06G032_SYSCTRL_USB_H2MODE (1<<1) #define R9A06G032_SYSCTRL_DMAMUX 0xA0 struct r9a06g032_gate { @@ -918,6 +920,29 @@ static void r9a06g032_clocks_del_clk_provider(void *data) of_clk_del_provider(data); } +static void __init r9a06g032_init_h2mode(struct r9a06g032_priv *clocks) +{ + struct device_node *usbf_np = NULL; + u32 usb; + + while ((usbf_np = of_find_compatible_node(usbf_np, NULL, + "renesas,rzn1-usbf"))) { + if (of_device_is_available(usbf_np)) + break; + } + + usb = readl(clocks->reg + R9A06G032_SYSCTRL_USB); + if (usbf_np) { + /* 1 host and 1 device mode */ + usb &= ~R9A06G032_SYSCTRL_USB_H2MODE; + of_node_put(usbf_np); + } else { + /* 2 hosts mode */ + usb |= R9A06G032_SYSCTRL_USB_H2MODE; + } + writel(usb, clocks->reg + R9A06G032_SYSCTRL_USB); +} + static int __init r9a06g032_clocks_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -947,6 +972,9 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev) clocks->reg = of_iomap(np, 0); if (WARN_ON(!clocks->reg)) return -ENOMEM; + + r9a06g032_init_h2mode(clocks); + for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); ++i) { const struct r9a06g032_clkdesc *d = &r9a06g032_clocks[i]; const char *parent_name = d->source ? -- cgit v1.2.3 From 1c052043c79af5f70e80e2acd4dd70904ae08666 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 11 Jan 2023 09:23:34 +0100 Subject: clk: renesas: cpg-mssr: Remove superfluous check in resume code When the code flow arrives at printing the error message in cpg_mssr_resume_noirq(), we know for sure that we are not running on an RZ/A Soc, as the code checked for that before. Fixes: ace342097768e35f ("clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/144a3e66d748c0c17f3524ac8fa6ece5bf5b6f1e.1673425314.git.geert+renesas@glider.be --- drivers/clk/renesas/renesas-cpg-mssr.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 5dce9779324d..202aeb232044 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -943,9 +943,8 @@ static int cpg_mssr_resume_noirq(struct device *dev) } if (!i) - dev_warn(dev, "Failed to enable %s%u[0x%x]\n", - priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? - "STB" : "SMSTP", reg, oldval & mask); + dev_warn(dev, "Failed to enable SMSTP%u[0x%x]\n", reg, + oldval & mask); } return 0; -- cgit v1.2.3 From 584d29912db27e56eaaccd225e283e1f429e4f83 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 8 Dec 2022 10:56:58 +0100 Subject: clk: renesas: r8a779g0: Add custom clock for PLL2 Currently the PLLs are modeled as fixed factor clocks, based on initial settings. However, enabling CPU boost clock rates requires increasing the PLL clock rates. Add a custom clock driver to model the PLL clocks on R-Car Gen4, and use it for PLL2 on R-Car V4H. This allows the Z clock (Cortex-A76 core clock) to request PLL rate changes, and enable boost mode for the High Performance mode. For now this is limited to integer multiplication modes. Note that the definition for CPG_PLLxCR0_NI uses the value for R-Car V4H. On R-Car S4-8, the integer and fractional multiplication fields are one bit larger resp. smaller, but R-Car S4-8 does not support High Performance mode. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/76a5952900a6e15604c640bc8a27762e0e936677.1670492384.git.geert+renesas@glider.be --- drivers/clk/renesas/r8a779g0-cpg-mssr.c | 14 +-- drivers/clk/renesas/rcar-gen4-cpg.c | 156 ++++++++++++++++++++++++++++++++ drivers/clk/renesas/rcar-gen4-cpg.h | 1 + 3 files changed, 164 insertions(+), 7 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index 745ff9214fe8..48d9f34bbf37 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -66,13 +66,13 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { DEF_INPUT("extalr", CLK_EXTALR), /* Internal Core Clocks */ - DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), - DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), - DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN), - DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), - DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN), - DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), - DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2_VAR, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), + DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN), + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), + DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c index e27832e5114f..c68d8b987054 100644 --- a/drivers/clk/renesas/rcar-gen4-cpg.c +++ b/drivers/clk/renesas/rcar-gen4-cpg.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include "renesas-cpg-mssr.h" @@ -27,6 +28,152 @@ static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initdata; static unsigned int cpg_clk_extalr __initdata; static u32 cpg_mode __initdata; +#define CPG_PLLECR 0x0820 /* PLL Enable Control Register */ + +#define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \ + (n) > 3 ? (n) + 1 : n)) /* PLLn Circuit Status */ + +#define CPG_PLL1CR0 0x830 /* PLLn Control Registers */ +#define CPG_PLL1CR1 0x8b0 +#define CPG_PLL2CR0 0x834 +#define CPG_PLL2CR1 0x8b8 +#define CPG_PLL3CR0 0x83c +#define CPG_PLL3CR1 0x8c0 +#define CPG_PLL4CR0 0x844 +#define CPG_PLL4CR1 0x8c8 +#define CPG_PLL6CR0 0x84c +#define CPG_PLL6CR1 0x8d8 + +#define CPG_PLLxCR0_KICK BIT(31) +#define CPG_PLLxCR0_NI GENMASK(27, 20) /* Integer mult. factor */ +#define CPG_PLLxCR0_SSMODE GENMASK(18, 16) /* PLL mode */ +#define CPG_PLLxCR0_SSMODE_FM BIT(18) /* Fractional Multiplication */ +#define CPG_PLLxCR0_SSMODE_DITH BIT(17) /* Frequency Dithering */ +#define CPG_PLLxCR0_SSMODE_CENT BIT(16) /* Center (vs. Down) Spread Dithering */ +#define CPG_PLLxCR0_SSFREQ GENMASK(14, 8) /* SSCG Modulation Frequency */ +#define CPG_PLLxCR0_SSDEPT GENMASK(6, 0) /* SSCG Modulation Depth */ + +#define SSMODE_FM BIT(2) /* Fractional Multiplication */ +#define SSMODE_DITHER BIT(1) /* Frequency Dithering */ +#define SSMODE_CENTER BIT(0) /* Center (vs. Down) Spread Dithering */ + +/* PLL Clocks */ +struct cpg_pll_clk { + struct clk_hw hw; + void __iomem *pllcr0_reg; + void __iomem *pllecr_reg; + u32 pllecr_pllst_mask; +}; + +#define to_pll_clk(_hw) container_of(_hw, struct cpg_pll_clk, hw) + +static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct cpg_pll_clk *pll_clk = to_pll_clk(hw); + unsigned int mult; + + mult = FIELD_GET(CPG_PLLxCR0_NI, readl(pll_clk->pllcr0_reg)) + 1; + + return parent_rate * mult * 2; +} + +static int cpg_pll_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned int min_mult, max_mult, mult; + unsigned long prate; + + prate = req->best_parent_rate * 2; + min_mult = max(div64_ul(req->min_rate, prate), 1ULL); + max_mult = min(div64_ul(req->max_rate, prate), 256ULL); + if (max_mult < min_mult) + return -EINVAL; + + mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); + mult = clamp(mult, min_mult, max_mult); + + req->rate = prate * mult; + return 0; +} + +static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct cpg_pll_clk *pll_clk = to_pll_clk(hw); + unsigned int mult; + u32 val; + + mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * 2); + mult = clamp(mult, 1U, 256U); + + if (readl(pll_clk->pllcr0_reg) & CPG_PLLxCR0_KICK) + return -EBUSY; + + cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_NI, + FIELD_PREP(CPG_PLLxCR0_NI, mult - 1)); + + /* + * Set KICK bit in PLLxCR0 to update hardware setting and wait for + * clock change completion. + */ + cpg_reg_modify(pll_clk->pllcr0_reg, 0, CPG_PLLxCR0_KICK); + + /* + * Note: There is no HW information about the worst case latency. + * + * Using experimental measurements, it seems that no more than + * ~45 µs are needed, independently of the CPU rate. + * Since this value might be dependent on external xtal rate, pll + * rate or even the other emulation clocks rate, use 1000 as a + * "super" safe value. + */ + return readl_poll_timeout(pll_clk->pllecr_reg, val, + val & pll_clk->pllecr_pllst_mask, 0, 1000); +} + +static const struct clk_ops cpg_pll_clk_ops = { + .recalc_rate = cpg_pll_clk_recalc_rate, + .determine_rate = cpg_pll_clk_determine_rate, + .set_rate = cpg_pll_clk_set_rate, +}; + +static struct clk * __init cpg_pll_clk_register(const char *name, + const char *parent_name, + void __iomem *base, + unsigned int cr0_offset, + unsigned int cr1_offset, + unsigned int index) + +{ + struct cpg_pll_clk *pll_clk; + struct clk_init_data init = {}; + struct clk *clk; + + pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); + if (!pll_clk) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &cpg_pll_clk_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + + pll_clk->hw.init = &init; + pll_clk->pllcr0_reg = base + cr0_offset; + pll_clk->pllecr_reg = base + CPG_PLLECR; + pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index); + + /* Disable Fractional Multiplication and Frequency Dithering */ + writel(0, base + cr1_offset); + cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_SSMODE, 0); + + clk = clk_register(NULL, &pll_clk->hw); + if (IS_ERR(clk)) + kfree(pll_clk); + + return clk; +} /* * Z0 Clock & Z1 Clock */ @@ -205,6 +352,15 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev, div = cpg_pll_config->pll1_div; break; + case CLK_TYPE_GEN4_PLL2_VAR: + /* + * PLL2 is implemented as a custom clock, to change the + * multiplier when cpufreq changes between normal and boost + * modes. + */ + return cpg_pll_clk_register(core->name, __clk_get_name(parent), + base, CPG_PLL2CR0, CPG_PLL2CR1, 2); + case CLK_TYPE_GEN4_PLL2: mult = cpg_pll_config->pll2_mult; div = cpg_pll_config->pll2_div; diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h index 0a0e3bdb3a66..006537e29e4e 100644 --- a/drivers/clk/renesas/rcar-gen4-cpg.h +++ b/drivers/clk/renesas/rcar-gen4-cpg.h @@ -13,6 +13,7 @@ enum rcar_gen4_clk_types { CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM, CLK_TYPE_GEN4_PLL1, CLK_TYPE_GEN4_PLL2, + CLK_TYPE_GEN4_PLL2_VAR, CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */ CLK_TYPE_GEN4_PLL3, CLK_TYPE_GEN4_PLL4, -- cgit v1.2.3 From c9baa3bbe909b8e4a263394afc80b5a499bd23c2 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 19 Jan 2023 01:52:16 +0000 Subject: clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMAC "sydm" is a bit name. Let's rename it to the common "sys-dmac". Signed-off-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/87tu0nz3xr.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779a0-cpg-mssr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index e02542ca24a0..fcc8279647a6 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -176,8 +176,8 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8), DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8), DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0), - DEF_MOD("sydm1", 709, R8A779A0_CLK_S1D2), - DEF_MOD("sydm2", 710, R8A779A0_CLK_S1D2), + DEF_MOD("sys-dmac1", 709, R8A779A0_CLK_S1D2), + DEF_MOD("sys-dmac2", 710, R8A779A0_CLK_S1D2), DEF_MOD("tmu0", 713, R8A779A0_CLK_CL16MCK), DEF_MOD("tmu1", 714, R8A779A0_CLK_S1D4), DEF_MOD("tmu2", 715, R8A779A0_CLK_S1D4), -- cgit v1.2.3 From 3797edf94b51387cc97fc5773d3e3e11c8d10dd4 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 19 Jan 2023 01:51:59 +0000 Subject: clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMAC "sydm" is a bit name. Let's rename it to the common "sys-dmac". Signed-off-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/87v8l3z3y8.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779g0-cpg-mssr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index 48d9f34bbf37..2bb9dea025ac 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -192,8 +192,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("scif3", 704, R8A779G0_CLK_SASYNCPERD4), DEF_MOD("scif4", 705, R8A779G0_CLK_SASYNCPERD4), DEF_MOD("sdhi", 706, R8A779G0_CLK_SD0), - DEF_MOD("sydm0", 709, R8A779G0_CLK_S0D6_PER), - DEF_MOD("sydm1", 710, R8A779G0_CLK_S0D6_PER), + DEF_MOD("sys-dmac0", 709, R8A779G0_CLK_S0D6_PER), + DEF_MOD("sys-dmac1", 710, R8A779G0_CLK_S0D6_PER), DEF_MOD("tmu0", 713, R8A779G0_CLK_SASYNCRT), DEF_MOD("tmu1", 714, R8A779G0_CLK_SASYNCPERD2), DEF_MOD("tmu2", 715, R8A779G0_CLK_SASYNCPERD2), -- cgit v1.2.3 From bd176e46e9c23f669b28630cc8f3fb1b89fd610e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 23 Jan 2023 19:31:24 +0100 Subject: clk: renesas: r8a779g0: Add CAN-FD clocks Add the CANFD core clock and the CANFD0 module clock, which are used by the CAN-FD Interface on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/a78f534bd80f170f3f1267f3270fdb3b7a73b5d4.1674498643.git.geert+renesas@glider.be --- drivers/clk/renesas/r8a779g0-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index 2bb9dea025ac..7fca11204f74 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -145,6 +145,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1), DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1), DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1), + DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1), DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884), @@ -163,6 +164,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC), DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC), DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC), + DEF_MOD("canfd0", 328, R8A779G0_CLK_SASYNCPERD2), DEF_MOD("dis0", 411, R8A779G0_CLK_VIOBUSD2), DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_VIOBUSD2), DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_VIOBUSD2), -- cgit v1.2.3 From b1dec4e78599a2ce5bf8557056cd6dd72e1096b0 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 2 Feb 2023 10:23:31 +0100 Subject: clk: renesas: rcar-gen3: Disable R-Car H3 ES1.* R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support for this SoC. Public users only have ES2 onwards. In addition to the ES1 specific removals, a check for it was added preventing the machine to boot further. It may otherwise inherit wrong clock settings from ES2 which could damage the hardware. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230202092332.2504-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/Kconfig | 2 +- drivers/clk/renesas/r8a7795-cpg-mssr.c | 126 +++------------------------------ drivers/clk/renesas/rcar-gen3-cpg.c | 17 +---- drivers/clk/renesas/renesas-cpg-mssr.c | 27 ------- drivers/clk/renesas/renesas-cpg-mssr.h | 14 ---- 5 files changed, 13 insertions(+), 173 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index cacaf9b87d26..37632a0659d8 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -22,7 +22,7 @@ config CLK_RENESAS select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793 select CLK_R8A7792 if ARCH_R8A7792 select CLK_R8A7794 if ARCH_R8A7794 - select CLK_R8A7795 if ARCH_R8A77950 || ARCH_R8A77951 + select CLK_R8A7795 if ARCH_R8A77951 select CLK_R8A77960 if ARCH_R8A77960 select CLK_R8A77961 if ARCH_R8A77961 select CLK_R8A77965 if ARCH_R8A77965 diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 301475c74f50..7a585a777d38 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -128,7 +128,6 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { }; static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { - DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */ DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1), DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1), DEF_MOD("tmu4", 121, R8A7795_CLK_S0D6), @@ -162,7 +161,6 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1), DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1), - DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */ DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1), DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1), @@ -187,28 +185,21 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), DEF_MOD("thermal", 522, R8A7795_CLK_CP), DEF_MOD("pwm", 523, R8A7795_CLK_S0D12), - DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */ DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2), DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2), DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2), DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1), DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1), - DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */ DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1), DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1), - DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */ DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1), DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1), - DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */ - DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */ DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1), - DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */ DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2), DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2), DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2), DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1), DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1), - DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */ DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1), DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1), DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2), @@ -221,7 +212,6 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1), DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1), DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1), - DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */ DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), DEF_MOD("csi40", 716, R8A7795_CLK_CSI0), @@ -350,103 +340,26 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { { 2, 192, 1, 192, 1, 32, }, }; -static const struct soc_device_attribute r8a7795es1[] __initconst = { +static const struct soc_device_attribute r8a7795_denylist[] __initconst = { { .soc_id = "r8a7795", .revision = "ES1.*" }, { /* sentinel */ } }; - - /* - * Fixups for R-Car H3 ES1.x - */ - -static const unsigned int r8a7795es1_mod_nullify[] __initconst = { - MOD_CLK_ID(326), /* USB-DMAC3-0 */ - MOD_CLK_ID(329), /* USB-DMAC3-1 */ - MOD_CLK_ID(700), /* EHCI/OHCI3 */ - MOD_CLK_ID(705), /* HS-USB-IF3 */ - -}; - -static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = { - { MOD_CLK_ID(118), R8A7795_CLK_S2D1 }, /* FDP1-1 */ - { MOD_CLK_ID(119), R8A7795_CLK_S2D1 }, /* FDP1-0 */ - { MOD_CLK_ID(121), R8A7795_CLK_S3D2 }, /* TMU4 */ - { MOD_CLK_ID(217), R8A7795_CLK_S3D1 }, /* SYS-DMAC2 */ - { MOD_CLK_ID(218), R8A7795_CLK_S3D1 }, /* SYS-DMAC1 */ - { MOD_CLK_ID(219), R8A7795_CLK_S3D1 }, /* SYS-DMAC0 */ - { MOD_CLK_ID(408), R8A7795_CLK_S3D1 }, /* INTC-AP */ - { MOD_CLK_ID(501), R8A7795_CLK_S3D1 }, /* AUDMAC1 */ - { MOD_CLK_ID(502), R8A7795_CLK_S3D1 }, /* AUDMAC0 */ - { MOD_CLK_ID(523), R8A7795_CLK_S3D4 }, /* PWM */ - { MOD_CLK_ID(601), R8A7795_CLK_S2D1 }, /* FCPVD2 */ - { MOD_CLK_ID(602), R8A7795_CLK_S2D1 }, /* FCPVD1 */ - { MOD_CLK_ID(603), R8A7795_CLK_S2D1 }, /* FCPVD0 */ - { MOD_CLK_ID(606), R8A7795_CLK_S2D1 }, /* FCPVB1 */ - { MOD_CLK_ID(607), R8A7795_CLK_S2D1 }, /* FCPVB0 */ - { MOD_CLK_ID(610), R8A7795_CLK_S2D1 }, /* FCPVI1 */ - { MOD_CLK_ID(611), R8A7795_CLK_S2D1 }, /* FCPVI0 */ - { MOD_CLK_ID(614), R8A7795_CLK_S2D1 }, /* FCPF1 */ - { MOD_CLK_ID(615), R8A7795_CLK_S2D1 }, /* FCPF0 */ - { MOD_CLK_ID(619), R8A7795_CLK_S2D1 }, /* FCPCS */ - { MOD_CLK_ID(621), R8A7795_CLK_S2D1 }, /* VSPD2 */ - { MOD_CLK_ID(622), R8A7795_CLK_S2D1 }, /* VSPD1 */ - { MOD_CLK_ID(623), R8A7795_CLK_S2D1 }, /* VSPD0 */ - { MOD_CLK_ID(624), R8A7795_CLK_S2D1 }, /* VSPBC */ - { MOD_CLK_ID(626), R8A7795_CLK_S2D1 }, /* VSPBD */ - { MOD_CLK_ID(630), R8A7795_CLK_S2D1 }, /* VSPI1 */ - { MOD_CLK_ID(631), R8A7795_CLK_S2D1 }, /* VSPI0 */ - { MOD_CLK_ID(804), R8A7795_CLK_S2D1 }, /* VIN7 */ - { MOD_CLK_ID(805), R8A7795_CLK_S2D1 }, /* VIN6 */ - { MOD_CLK_ID(806), R8A7795_CLK_S2D1 }, /* VIN5 */ - { MOD_CLK_ID(807), R8A7795_CLK_S2D1 }, /* VIN4 */ - { MOD_CLK_ID(808), R8A7795_CLK_S2D1 }, /* VIN3 */ - { MOD_CLK_ID(809), R8A7795_CLK_S2D1 }, /* VIN2 */ - { MOD_CLK_ID(810), R8A7795_CLK_S2D1 }, /* VIN1 */ - { MOD_CLK_ID(811), R8A7795_CLK_S2D1 }, /* VIN0 */ - { MOD_CLK_ID(812), R8A7795_CLK_S3D2 }, /* EAVB-IF */ - { MOD_CLK_ID(820), R8A7795_CLK_S2D1 }, /* IMR3 */ - { MOD_CLK_ID(821), R8A7795_CLK_S2D1 }, /* IMR2 */ - { MOD_CLK_ID(822), R8A7795_CLK_S2D1 }, /* IMR1 */ - { MOD_CLK_ID(823), R8A7795_CLK_S2D1 }, /* IMR0 */ - { MOD_CLK_ID(905), R8A7795_CLK_CP }, /* GPIO7 */ - { MOD_CLK_ID(906), R8A7795_CLK_CP }, /* GPIO6 */ - { MOD_CLK_ID(907), R8A7795_CLK_CP }, /* GPIO5 */ - { MOD_CLK_ID(908), R8A7795_CLK_CP }, /* GPIO4 */ - { MOD_CLK_ID(909), R8A7795_CLK_CP }, /* GPIO3 */ - { MOD_CLK_ID(910), R8A7795_CLK_CP }, /* GPIO2 */ - { MOD_CLK_ID(911), R8A7795_CLK_CP }, /* GPIO1 */ - { MOD_CLK_ID(912), R8A7795_CLK_CP }, /* GPIO0 */ - { MOD_CLK_ID(918), R8A7795_CLK_S3D2 }, /* I2C6 */ - { MOD_CLK_ID(919), R8A7795_CLK_S3D2 }, /* I2C5 */ - { MOD_CLK_ID(927), R8A7795_CLK_S3D2 }, /* I2C4 */ - { MOD_CLK_ID(928), R8A7795_CLK_S3D2 }, /* I2C3 */ -}; - - - /* - * Fixups for R-Car H3 ES2.x - */ - -static const unsigned int r8a7795es2_mod_nullify[] __initconst = { - MOD_CLK_ID(117), /* FDP1-2 */ - MOD_CLK_ID(327), /* USB3-IF1 */ - MOD_CLK_ID(600), /* FCPVD3 */ - MOD_CLK_ID(609), /* FCPVI2 */ - MOD_CLK_ID(613), /* FCPF2 */ - MOD_CLK_ID(616), /* FCPCI1 */ - MOD_CLK_ID(617), /* FCPCI0 */ - MOD_CLK_ID(620), /* VSPD3 */ - MOD_CLK_ID(629), /* VSPI2 */ - MOD_CLK_ID(713), /* CSI21 */ -}; - static int __init r8a7795_cpg_mssr_init(struct device *dev) { const struct rcar_gen3_cpg_pll_config *cpg_pll_config; u32 cpg_mode; int error; + /* + * We panic here to ensure removed SoCs and clk updates are always in + * sync to avoid overclocking damages. The panic can only be seen with + * commandline args 'earlycon keep_bootcon'. But these SoCs were for + * developers only anyhow. + */ + if (soc_device_match(r8a7795_denylist)) + panic("SoC not supported anymore!\n"); + error = rcar_rst_read_mode_pins(&cpg_mode); if (error) return error; @@ -457,25 +370,6 @@ static int __init r8a7795_cpg_mssr_init(struct device *dev) return -EINVAL; } - if (soc_device_match(r8a7795es1)) { - cpg_core_nullify_range(r8a7795_core_clks, - ARRAY_SIZE(r8a7795_core_clks), - R8A7795_CLK_S0D2, R8A7795_CLK_S0D12); - mssr_mod_nullify(r8a7795_mod_clks, - ARRAY_SIZE(r8a7795_mod_clks), - r8a7795es1_mod_nullify, - ARRAY_SIZE(r8a7795es1_mod_nullify)); - mssr_mod_reparent(r8a7795_mod_clks, - ARRAY_SIZE(r8a7795_mod_clks), - r8a7795es1_mod_reparent, - ARRAY_SIZE(r8a7795es1_mod_reparent)); - } else { - mssr_mod_nullify(r8a7795_mod_clks, - ARRAY_SIZE(r8a7795_mod_clks), - r8a7795es2_mod_nullify, - ARRAY_SIZE(r8a7795es2_mod_nullify)); - } - return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); } diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index e668f23c75e7..b3ef62fa612e 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -310,19 +310,10 @@ static unsigned int cpg_clk_extalr __initdata; static u32 cpg_mode __initdata; static u32 cpg_quirks __initdata; -#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */ #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ static const struct soc_device_attribute cpg_quirks_match[] __initconst = { - { - .soc_id = "r8a7795", .revision = "ES1.0", - .data = (void *)(PLL_ERRATA | RCKCR_CKSEL), - }, - { - .soc_id = "r8a7795", .revision = "ES1.*", - .data = (void *)(RCKCR_CKSEL), - }, { .soc_id = "r8a7796", .revision = "ES1.0", .data = (void *)(RCKCR_CKSEL), @@ -355,9 +346,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, * multiplier when cpufreq changes between normal and boost * modes. */ - mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2; return cpg_pll_clk_register(core->name, __clk_get_name(parent), - base, mult, CPG_PLL0CR, 0); + base, 2, CPG_PLL0CR, 0); case CLK_TYPE_GEN3_PLL1: mult = cpg_pll_config->pll1_mult; @@ -370,9 +360,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, * multiplier when cpufreq changes between normal and boost * modes. */ - mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2; return cpg_pll_clk_register(core->name, __clk_get_name(parent), - base, mult, CPG_PLL2CR, 2); + base, 2, CPG_PLL2CR, 2); case CLK_TYPE_GEN3_PLL3: mult = cpg_pll_config->pll3_mult; @@ -388,8 +377,6 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, */ value = readl(base + CPG_PLL4CR); mult = (((value >> 24) & 0x7f) + 1) * 2; - if (cpg_quirks & PLL_ERRATA) - mult *= 2; break; case CLK_TYPE_GEN3_SDH: diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 202aeb232044..b9f210437ddf 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -1113,19 +1113,6 @@ static int __init cpg_mssr_init(void) subsys_initcall(cpg_mssr_init); -void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks, - unsigned int num_core_clks, - unsigned int first_clk, - unsigned int last_clk) -{ - unsigned int i; - - for (i = 0; i < num_core_clks; i++) - if (core_clks[i].id >= first_clk && - core_clks[i].id <= last_clk) - core_clks[i].name = NULL; -} - void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks, unsigned int num_mod_clks, const unsigned int *clks, unsigned int n) @@ -1139,19 +1126,5 @@ void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks, } } -void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks, - unsigned int num_mod_clks, - const struct mssr_mod_reparent *clks, - unsigned int n) -{ - unsigned int i, j; - - for (i = 0, j = 0; i < num_mod_clks && j < n; i++) - if (mod_clks[i].id == clks[j].clk) { - mod_clks[i].parent = clks[j].parent; - j++; - } -} - MODULE_DESCRIPTION("Renesas CPG/MSSR Driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 1c3c057d17f5..80c5b462924a 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -187,21 +187,7 @@ void __init cpg_mssr_early_init(struct device_node *np, /* * Helpers for fixing up clock tables depending on SoC revision */ - -struct mssr_mod_reparent { - unsigned int clk, parent; -}; - - -extern void cpg_core_nullify_range(struct cpg_core_clk *core_clks, - unsigned int num_core_clks, - unsigned int first_clk, - unsigned int last_clk); extern void mssr_mod_nullify(struct mssr_mod_clk *mod_clks, unsigned int num_mod_clks, const unsigned int *clks, unsigned int n); -extern void mssr_mod_reparent(struct mssr_mod_clk *mod_clks, - unsigned int num_mod_clks, - const struct mssr_mod_reparent *clks, - unsigned int n); #endif -- cgit v1.2.3