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authorGravatar Haibo Chen <haibo.chen@nxp.com> 2023-03-22 17:04:50 +0800
committerGravatar Mark Brown <broonie@kernel.org> 2023-03-22 13:17:42 +0000
commit1ab09f1d070c4774175dab95e55d2b72c2a054ab (patch)
tree969bbfbda8c73db1f88e12debfb825438199b065
parentspi: sprd: Convert to platform remove callback (diff)
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spi: spi-nxp-fspi: correct the comment for the DLL config
Current DLL config is just to use the default setting, this means enable the DLL override mode, and use 1 fixed delay cell in the DLL delay chain, not means "reset" the DLL, so correct this to avoid confuse. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Link: https://lore.kernel.org/r/20230322090451.3179431-1-haibo.chen@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--drivers/spi/spi-nxp-fspi.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 76168cc1e00d..6735c22b9137 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -997,7 +997,11 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f)
/* Disable the module */
fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
- /* Reset the DLL register to default value */
+ /*
+ * Config the DLL register to default value, enable the slave clock delay
+ * line delay cell override mode, and use 1 fixed delay cell in DLL delay
+ * chain, this is the suggested setting when clock rate < 100MHz.
+ */
fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);