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authorGravatar Josua Mayer <josua@solid-run.com> 2023-10-01 12:32:56 +0200
committerGravatar Shawn Guo <shawnguo@kernel.org> 2023-10-10 11:06:00 +0800
commit2f2900176b444156740f13241f71a0a4dca0fba6 (patch)
tree2971bee85606ee6707f2f5083387f7b1f7a84105
parentarm64: dts: imx93: update gpio node (diff)
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arm64: dts: lx2160a: describe the SerDes block #2
Add description for the LX2160A second SerDes block. It is functionally identical to the first one already added in commit 3cbe93a1f540 ("arch: arm64: dts: lx2160a: describe the SerDes block #1"). The SerDes driver currently updates the registers of all 8 lanes by default during probe. Because currently this driver only supports configuration of network protocols, this can lead to problems with certain configurations. Set status property to "disabled" by default so that existing boards are not impacted. Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index ea6a94b57aeb..f176ca2e244e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -626,6 +626,13 @@
#phy-cells = <1>;
};
+ serdes_2: phy@1eb0000 {
+ compatible = "fsl,lynx-28g";
+ reg = <0x0 0x1eb0000 0x0 0x1e30>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <10>;