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| author |  Michal Wajdeczko <michal.wajdeczko@intel.com>
| 2023-12-18 17:53:36 +0100 |
|---|---|---|
| committer |  Rodrigo Vivi <rodrigo.vivi@intel.com>
| 2023-12-21 16:31:29 -0500 |
| commit | 54020e2b406d8d4be6d79409957f2130e93b4fa3 (patch) | |
| tree | cd875afe9f12fa1af063e2ff45764208725b95a6 | |
| parent | drm/xe: Add command MI_LOAD_REGISTER_MEM (diff) | |
| download | linux-54020e2b406d8d4be6d79409957f2130e93b4fa3.tar.gz linux-54020e2b406d8d4be6d79409957f2130e93b4fa3.tar.bz2 linux-54020e2b406d8d4be6d79409957f2130e93b4fa3.zip | |
drm/xe: Define registers used by memory based irq processing
The RING_INT_SRC_RPT_PTR register points to a cacheline in memory
to which an engine must report as source of interrupt prior to
generating an interrupt to the host.
The RING_INT_STATUS_RPT_PTR register points to the first cacheline
of the Interrupt Status Report (ISR) page (4KB) in graphics memory
to which all engines report their interrupt status.
The RING_IMR register has the interrupt enables and interrupt masks
for an engine.
We will refer to these registers shortly.
Bspec: 45963, 45964, 45965
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231214185955.1791-3-michal.wajdeczko@intel.com
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_engine_regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h index 5592774fc690..bd9c956f48a7 100644 --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h @@ -75,7 +75,9 @@ #define FF_THREAD_MODE(base) XE_REG((base) + 0xa0) #define FF_TESSELATION_DOP_GATE_DISABLE BIT(19) +#define RING_INT_SRC_RPT_PTR(base) XE_REG((base) + 0xa4) #define RING_IMR(base) XE_REG((base) + 0xa8) +#define RING_INT_STATUS_RPT_PTR(base) XE_REG((base) + 0xac) #define RING_EIR(base) XE_REG((base) + 0xb0) #define RING_EMR(base) XE_REG((base) + 0xb4) |