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author | Tudor Ambarus <tudor.ambarus@linaro.org> | 2024-01-19 10:45:24 +0000 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-01-27 19:05:19 -0800 |
commit | 6e1e48b6ef2613ff4c28a34f7a57c29a4367ad87 (patch) | |
tree | 3cfab20fa8597445ef23e80d5e66a271e4f5c825 | |
parent | tty: serial: samsung: change return type for s3c24xx_serial_rx_fifocnt() (diff) | |
download | linux-6e1e48b6ef2613ff4c28a34f7a57c29a4367ad87.tar.gz linux-6e1e48b6ef2613ff4c28a34f7a57c29a4367ad87.tar.bz2 linux-6e1e48b6ef2613ff4c28a34f7a57c29a4367ad87.zip |
tty: serial: samsung: shrink the clock selection to 8 clocks
<linux/serial_s3c.h> provides a clock selection pool of maximum 4 clocks.
Update the driver to consider a pool selection of maximum 8 clocks.
u8 is large enough to allow more clocks than are supported by the driver
now, and not too big to cause spanning of ``struct s3c24xx_uart_info``
through 2 cachelines when compiled for arm64. The goal is to reduce the
memory footprint of ``struct s3c24xx_uart_info``.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240119104526.1221243-18-tudor.ambarus@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r-- | drivers/tty/serial/samsung_tty.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 149f618e22ce..c429029c0207 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -81,11 +81,11 @@ struct s3c24xx_uart_info { unsigned long tx_fifomask; unsigned long tx_fifoshift; unsigned long tx_fifofull; - unsigned int def_clk_sel; - unsigned long num_clks; unsigned long clksel_mask; unsigned long clksel_shift; unsigned long ucon_mask; + u8 def_clk_sel; + u8 num_clks; u8 iotype; /* uart port features */ @@ -1340,7 +1340,7 @@ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, #define MAX_CLK_NAME_LENGTH 15 -static inline int s3c24xx_serial_getsource(struct uart_port *port) +static inline u8 s3c24xx_serial_getsource(struct uart_port *port) { const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); u32 ucon; @@ -1353,8 +1353,7 @@ static inline int s3c24xx_serial_getsource(struct uart_port *port) return ucon >> info->clksel_shift; } -static void s3c24xx_serial_setsource(struct uart_port *port, - unsigned int clk_sel) +static void s3c24xx_serial_setsource(struct uart_port *port, u8 clk_sel) { const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); u32 ucon; @@ -1373,14 +1372,15 @@ static void s3c24xx_serial_setsource(struct uart_port *port, static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport, unsigned int req_baud, struct clk **best_clk, - unsigned int *clk_num) + u8 *clk_num) { const struct s3c24xx_uart_info *info = ourport->info; struct clk *clk; unsigned long rate; - unsigned int cnt, baud, quot, best_quot = 0; + unsigned int baud, quot, best_quot = 0; char clkname[MAX_CLK_NAME_LENGTH]; int calc_deviation, deviation = (1 << 30) - 1; + u8 cnt; for (cnt = 0; cnt < info->num_clks; cnt++) { /* Keep selected clock if provided */ @@ -1473,9 +1473,10 @@ static void s3c24xx_serial_set_termios(struct uart_port *port, struct s3c24xx_uart_port *ourport = to_ourport(port); struct clk *clk = ERR_PTR(-EINVAL); unsigned long flags; - unsigned int baud, quot, clk_sel = 0; + unsigned int baud, quot; unsigned int udivslot = 0; u32 ulcon, umcon; + u8 clk_sel = 0; /* * We don't support modem control lines. @@ -1776,10 +1777,9 @@ static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport) struct device *dev = ourport->port.dev; const struct s3c24xx_uart_info *info = ourport->info; char clk_name[MAX_CLK_NAME_LENGTH]; - unsigned int clk_sel; struct clk *clk; - int clk_num; int ret; + u8 clk_sel, clk_num; clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel; for (clk_num = 0; clk_num < info->num_clks; clk_num++) { @@ -2287,9 +2287,9 @@ s3c24xx_serial_get_options(struct uart_port *port, int *baud, { struct clk *clk; unsigned long rate; - unsigned int clk_sel; u32 ulcon, ucon, ubrdiv; char clk_name[MAX_CLK_NAME_LENGTH]; + u8 clk_sel; ulcon = rd_regl(port, S3C2410_ULCON); ucon = rd_regl(port, S3C2410_UCON); |