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| author |  Yangyang Li <liyangyang20@huawei.com>
| 2021-04-02 17:07:28 +0800 |
|---|---|---|
| committer |  Jason Gunthorpe <jgg@nvidia.com>
| 2021-04-08 16:08:21 -0300 |
| commit | 714a597baab099e728307768e3b5c3b82d7b2ce3 (patch) | |
| tree | db12b0f9a906faf61de46a81037139ebb50978be | |
| parent | RDMA/hns: Fix missing assignment of max_inline_data (diff) | |
| download | linux-714a597baab099e728307768e3b5c3b82d7b2ce3.tar.gz linux-714a597baab099e728307768e3b5c3b82d7b2ce3.tar.bz2 linux-714a597baab099e728307768e3b5c3b82d7b2ce3.zip | |
RDMA/hns: Delete redundant condition judgment related to eq
The register value related to the eq interrupt depends only on
enable_flag, so the redundant condition judgment is deleted.
Fixes: a5073d6054f7 ("RDMA/hns: Add eq support of hip08")
Link: https://lore.kernel.org/r/1617354454-47840-4-git-send-email-liweihang@huawei.com
Signed-off-by: Yangyang Li <liyangyang20@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
| -rw-r--r-- | drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 27 |
1 files changed, 6 insertions, 21 deletions
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index 969e2c310772..e222bf38ef2d 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -6063,31 +6063,16 @@ static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) } static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, - int eq_num, int enable_flag) + int eq_num, u32 enable_flag) { int i; - if (enable_flag == EQ_ENABLE) { - for (i = 0; i < eq_num; i++) - roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + - i * EQ_REG_OFFSET, - HNS_ROCE_V2_VF_EVENT_INT_EN_M); - - roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, - HNS_ROCE_V2_VF_ABN_INT_EN_M); - roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, - HNS_ROCE_V2_VF_ABN_INT_CFG_M); - } else { - for (i = 0; i < eq_num; i++) - roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + - i * EQ_REG_OFFSET, - HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0); + for (i = 0; i < eq_num; i++) + roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + + i * EQ_REG_OFFSET, enable_flag); - roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, - HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0); - roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, - HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0); - } + roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); + roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); } static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn) |