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| author |  Andre Przywara <andre.przywara@arm.com>
| 2017-11-25 12:12:30 +0000 |
|---|---|---|
| committer |  Linus Walleij <linus.walleij@linaro.org>
| 2017-11-30 16:48:54 +0100 |
| commit | 7c5c2c2d18d778e51fd8b899965097168306031c (patch) | |
| tree | 4282688a294cc22cf771dc57feab4a28e0beb4e3 | |
| parent | pinctrl: sunxi: Fix A80 interrupt pin bank (diff) | |
| download | linux-7c5c2c2d18d778e51fd8b899965097168306031c.tar.gz linux-7c5c2c2d18d778e51fd8b899965097168306031c.tar.bz2 linux-7c5c2c2d18d778e51fd8b899965097168306031c.zip | |
pinctrl: sunxi: Fix A64 UART mux value
To use pin PF4 as the RX signal of UART0, we have to write 0b011 into
the respective pin controller register.
Fix the wrong value we had in our table so far.
Fixes: 96851d391d02 ("drivers: pinctrl: add driver for Allwinner A64 SoC")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| -rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c index 4f2a726bbaeb..f5f77432ce6f 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c @@ -428,7 +428,7 @@ static const struct sunxi_desc_pin a64_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ - SUNXI_FUNCTION(0x4, "uart0")), /* RX */ + SUNXI_FUNCTION(0x3, "uart0")), /* RX */ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), |