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| author |  Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
| 2020-04-14 18:48:41 +0200 |
|---|---|---|
| committer |  Jonathan Corbet <corbet@lwn.net>
| 2020-04-20 15:45:23 -0600 |
| commit | cfa204984d57ef205b09c7f6db9b562821b51dbd (patch) | |
| tree | e2d2501484244eeb263930bb8e094275c8b06473 /Documentation/admin-guide/ras.rst | |
| parent | docs: pci: boot-interrupts.rst: improve html output (diff) | |
| download | linux-cfa204984d57ef205b09c7f6db9b562821b51dbd.tar.gz linux-cfa204984d57ef205b09c7f6db9b562821b51dbd.tar.bz2 linux-cfa204984d57ef205b09c7f6db9b562821b51dbd.zip | |
docs: ras: get rid of some warnings
Sphinx produce some warnings due to a bad table format:
Documentation/admin-guide/ras.rst:358: WARNING: Definition list ends without a blank line; unexpected unindent.
Documentation/admin-guide/ras.rst:358: WARNING: Definition list ends without a blank line; unexpected unindent.
Documentation/admin-guide/ras.rst:363: WARNING: Definition list ends without a blank line; unexpected unindent.
Documentation/admin-guide/ras.rst:363: WARNING: Definition list ends without a blank line; unexpected unindent.
Rearrange the things there in order to supress the warnings
while being precise at the Sphinx output about how ranks are
mapped into csrows.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lore.kernel.org/r/9e1bb44d6dbedb5b6f049d081b47da1f9620de16.1586881715.git.mchehab+huawei@kernel.org
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'Documentation/admin-guide/ras.rst')
| -rw-r--r-- | Documentation/admin-guide/ras.rst | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/Documentation/admin-guide/ras.rst b/Documentation/admin-guide/ras.rst index 0310db624964..22b31bc7e129 100644 --- a/Documentation/admin-guide/ras.rst +++ b/Documentation/admin-guide/ras.rst @@ -351,15 +351,17 @@ controllers. The following example will assume 2 channels: +------------+-----------+-----------+ | | ``ch0`` | ``ch1`` | +============+===========+===========+ - | ``csrow0`` | DIMM_A0 | DIMM_B0 | - | | rank0 | rank0 | - +------------+ - | - | + | |**DIMM_A0**|**DIMM_B0**| + +------------+-----------+-----------+ + | ``csrow0`` | rank0 | rank0 | + +------------+-----------+-----------+ | ``csrow1`` | rank1 | rank1 | +------------+-----------+-----------+ - | ``csrow2`` | DIMM_A1 | DIMM_B1 | - | | rank0 | rank0 | - +------------+ - | - | - | ``csrow3`` | rank1 | rank1 | + | |**DIMM_A1**|**DIMM_B1**| + +------------+-----------+-----------+ + | ``csrow2`` | rank0 | rank0 | + +------------+-----------+-----------+ + | ``csrow3`` | rank1 | rank1 | +------------+-----------+-----------+ In the above example, there are 4 physical slots on the motherboard |