diff options
| author |  Ley Foon Tan <leyfoon.tan@starfivetech.com>
| 2024-03-07 01:23:30 +0800 |
|---|---|---|
| committer |  Daniel Lezcano <daniel.lezcano@linaro.org>
| 2024-03-13 12:08:59 +0100 |
| commit | 8248ca30ef89f9cc74ace62ae1b9a22b5f16736c (patch) | |
| tree | 6c773ccc00cdb6cbd2a49e64a9b282776e245c3e /Documentation/devicetree/bindings/csky | |
| parent | dt-bindings: timer: Add support for cadence TTC PWM (diff) | |
| download | linux-8248ca30ef89f9cc74ace62ae1b9a22b5f16736c.tar.gz linux-8248ca30ef89f9cc74ace62ae1b9a22b5f16736c.tar.bz2 linux-8248ca30ef89f9cc74ace62ae1b9a22b5f16736c.zip | |
clocksource/drivers/timer-riscv: Clear timer interrupt on timer initialization
In the RISC-V specification, the stimecmp register doesn't have a default
value. To prevent the timer interrupt from being triggered during timer
initialization, clear the timer interrupt by writing stimecmp with a
maximum value.
Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available")
Cc: <stable@vger.kernel.org>
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20240306172330.255844-1-leyfoon.tan@starfivetech.com
Diffstat (limited to 'Documentation/devicetree/bindings/csky')
0 files changed, 0 insertions, 0 deletions