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| author |  Michal Simek <michal.simek@amd.com>
| 2023-11-06 12:37:47 +0100 |
|---|---|---|
| committer |  Palmer Dabbelt <palmer@rivosinc.com>
| 2023-12-20 07:15:00 -0800 |
| commit | 4a6b93f5629668d1dc8fa5945657fdd124629c55 (patch) | |
| tree | a8c66e1e3b2a4e68dc654cb9df3d540793115a0a /Documentation/devicetree/bindings/riscv | |
| parent | Merge patch series "riscv: report more ISA extensions through hwprobe" (diff) | |
| download | linux-4a6b93f5629668d1dc8fa5945657fdd124629c55.tar.gz linux-4a6b93f5629668d1dc8fa5945657fdd124629c55.tar.bz2 linux-4a6b93f5629668d1dc8fa5945657fdd124629c55.zip | |
dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatible
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/d442d916204d26f82c1c3a924a4cdfb117960e1b.1699270661.git.michal.simek@amd.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation/devicetree/bindings/riscv')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index f392e367d673..23646b684ea2 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -32,6 +32,7 @@ properties: oneOf: - items: - enum: + - amd,mbv32 - andestech,ax45mp - canaan,k210 - sifive,bullet0 |