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authorGravatar Peng Fan <peng.fan@nxp.com> 2022-09-02 19:12:06 +0800
committerGravatar Daniel Lezcano <daniel.lezcano@linaro.org> 2022-09-20 10:49:46 +0200
commit061f42748d0639647636b7a48d71951e8d92720a (patch)
tree2e5986129334ca66e66c9b0694ce2bb0cb14e880 /Documentation/devicetree/bindings/timer
parentclocksource/drivers/timer-ti-dm: Get clock in probe with devm_clk_get() (diff)
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dt-bindings: timer: nxp,sysctr-timer: add nxp,no-divider property
The base clock input to system counter is internally divided by 3 in previous design, but there is change that no divider now. So add a property to indicate that. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220902111207.2902493-2-peng.fan@oss.nxp.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/timer')
-rw-r--r--Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml4
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml
index 830211c55b4a..2b9653dafab8 100644
--- a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml
@@ -32,6 +32,10 @@ properties:
clock-names:
const: per
+ nxp,no-divider:
+ description: if present, means there is no internal base clk divider.
+ type: boolean
+
required:
- compatible
- reg