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| author |  Jeremy J. Peper <jeremy@jeremypeper.com>
| 2023-03-17 10:43:46 -0500 |
|---|---|---|
| committer |  Arnd Bergmann <arnd@arndb.de>
| 2023-04-18 17:04:28 +0200 |
| commit | 4b01f735a619ae535d4459aec3b070c9336e56b4 (patch) | |
| tree | f6daa4d1d09f90d334ca60dac0a106710681edd3 /arch/arm/mach-mv78xx0/mv78xx0.h | |
| parent | ARM: mv78xx0: set the correct driver for the i2c RTC (diff) | |
| download | linux-4b01f735a619ae535d4459aec3b070c9336e56b4.tar.gz linux-4b01f735a619ae535d4459aec3b070c9336e56b4.tar.bz2 linux-4b01f735a619ae535d4459aec3b070c9336e56b4.zip | |
ARM: mv78xx0: add code to enable XOR and CRYPTO engines on mv78xx0
Adding missing code/values required to enable the XOR and CESA engines for this SoC
Signed-off-by: Jeremy J. Peper <jeremy@jeremypeper.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-mv78xx0/mv78xx0.h')
| -rw-r--r-- | arch/arm/mach-mv78xx0/mv78xx0.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-mv78xx0/mv78xx0.h b/arch/arm/mach-mv78xx0/mv78xx0.h index 3f19bef7d7ac..88efb1e44142 100644 --- a/arch/arm/mach-mv78xx0/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/mv78xx0.h @@ -49,9 +49,15 @@ #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000) #define MV78XX0_REGS_SIZE SZ_1M +#define MV78XX0_SRAM_PHYS_BASE (0xf2200000) +#define MV78XX0_SRAM_SIZE SZ_8K + #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 #define MV78XX0_PCIE_MEM_SIZE 0x30000000 +#define MV78XX0_MBUS_SRAM_TARGET 0x09 +#define MV78XX0_MBUS_SRAM_ATTR 0x00 + /* * Core-specific peripheral registers. */ @@ -98,6 +104,8 @@ #define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000) #define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000) +#define XOR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x60900) + #define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000) #define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000) @@ -106,6 +114,8 @@ #define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000) #define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000) +#define CRYPTO_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x90000) + #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000) /* |