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| author |  Janusz Krzysztofik <jmkrzyszt@gmail.com>
| 2022-04-10 15:07:56 +0200 |
|---|---|---|
| committer |  Arnd Bergmann <arnd@arndb.de>
| 2022-04-22 11:08:56 +0200 |
| commit | e9bdc3d4f59c5c19284311994e7f80e3fcc952b6 (patch) | |
| tree | eb02f40f5f2530a4254fa3f369ee5cad7fa26546 /arch/arm/mach-omap1/clock_data.c | |
| parent | ARM: OMAP1: clock: Remove unused code (diff) | |
| download | linux-e9bdc3d4f59c5c19284311994e7f80e3fcc952b6.tar.gz linux-e9bdc3d4f59c5c19284311994e7f80e3fcc952b6.tar.bz2 linux-e9bdc3d4f59c5c19284311994e7f80e3fcc952b6.zip | |
ARM: OMAP1: clock: Remove noop code
There are some OMAP1 clock code bits that have no effect:
- crystal_type variable is set to 0 but never changed, then
crystal_type == 2 condition is never true and ck_ref.rate never set to
19200000,
- clk->ops->allow_idle() is called from omap_clk_enable_autoidle_all() but
that op is not configured for any clock, then the function does nothing
and the op field is not needed,
- ENABLE_ON_INIT flag is set for some clocks but is never checked by any
code, then not needed.
Drop that code.
Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-omap1/clock_data.c')
| -rw-r--r-- | arch/arm/mach-omap1/clock_data.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 57d3752babf8..9b9c9fcc61c2 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -92,8 +92,7 @@ static struct arm_idlect1_clk ck_dpll1out = { .name = "ck_dpll1out", .ops = &clkops_generic, .parent = &ck_dpll1, - .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT | - ENABLE_ON_INIT, + .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_CKOUT_ARM, .recalc = &followparent_recalc, @@ -146,7 +145,6 @@ static struct clk arm_gpio_ck = { .name = "ick", .ops = &clkops_generic, .parent = &ck_dpll1, - .flags = ENABLE_ON_INIT, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_GPIOCK, .recalc = &followparent_recalc, @@ -316,7 +314,6 @@ static struct clk tc2_ck = { .name = "tc2_ck", .ops = &clkops_generic, .parent = &tc_ck.clk, - .flags = ENABLE_ON_INIT, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), .enable_bit = EN_TC2_CK, .recalc = &followparent_recalc, @@ -762,7 +759,6 @@ u32 cpu_mask; int __init omap1_clk_init(void) { struct omap_clk *c; - int crystal_type = 0; /* Default 12 MHz */ u32 reg; #ifdef CONFIG_DEBUG_LL @@ -810,8 +806,6 @@ int __init omap1_clk_init(void) if (cpu_is_omap7xx()) ck_ref.rate = 13000000; - if (cpu_is_omap16xx() && crystal_type == 2) - ck_ref.rate = 19200000; pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), |