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authorGravatar Geert Uytterhoeven <geert+renesas@glider.be> 2017-09-01 10:37:45 +0200
committerGravatar Simon Horman <horms+renesas@verge.net.au> 2017-09-18 08:10:44 +0200
commit3fd45a136ff61bb54deab70fb2d534a85e40481f (patch)
tree1badca61f678bc8351f641515d85a6225cd52d61 /arch/arm/mach-shmobile/headsmp-apmu.S
parentARM: Add definition for monitor mode (diff)
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ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15
On Cortex-A7, the arch timer CNTVOFF register is uninitialized. Ideally it should be initialized by the boot loader, but it isn't. For the boot CPU, CNTVOFF is initialized by Linux since commit 9ce3fa6816c2fb59 ("ARM: shmobile: rcar-gen2: Add CA7 arch_timer initialization for r8a7794"). For secondary CPU cores, no such initialization is done. Hence when enabling SMP on r8a7794, the kernel log is spammed with: WARNING: Underflow in clocksource 'arch_sys_counter' observed, time update ignored. Please report this, consider using a different clocksource, if possible. Your kernel is probably still fine. As Marc Zyngier pointed out that Cortex-A15 and Cortex-A7 are similar with respect to CNTVOFF, we have been very lucky this just worked on R-Car Gen2 SoCs with Cortex-A15 cores. To fix this: - Move the existing inline asm code to initialize CNTVOFF to an assembler source file (adding comments and replacing hardcoded constants by definitions in the process), so it can be reused, - Perform the initialization of CNTVOFF on the boot CPU (Cortex-A15 or Cortex-A7) on all R-Car Gen2 and RZ/G1 parts, - Wrap the standard secondary_startup() routine inside a routine which initializes CNTVOFF. Based on patches by Hisashi Nakamura in the BSP. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/mach-shmobile/headsmp-apmu.S')
-rw-r--r--arch/arm/mach-shmobile/headsmp-apmu.S37
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S b/arch/arm/mach-shmobile/headsmp-apmu.S
new file mode 100644
index 000000000000..db4743d2bf91
--- /dev/null
+++ b/arch/arm/mach-shmobile/headsmp-apmu.S
@@ -0,0 +1,37 @@
+/*
+ * SMP support for APMU based systems with Cortex A7/A15
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ENTRY(shmobile_init_cntvoff)
+ /*
+ * CNTVOFF has to be initialized either from non-secure Hypervisor
+ * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+ * then it should be handled by the secure code
+ */
+ cps #MON_MODE
+ mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
+ orr r0, r1, #1
+ mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
+ instr_sync
+ mov r0, #0
+ mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */
+ instr_sync
+ mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
+ instr_sync
+ cps #SVC_MODE
+ ret lr
+ENDPROC(shmobile_init_cntvoff)
+
+ENTRY(shmobile_boot_apmu)
+ bl shmobile_init_cntvoff
+ b secondary_startup
+ENDPROC(shmobile_boot_apmu)