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author | 2019-01-09 14:36:34 +0000 | |
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committer | 2019-10-26 10:44:49 +0100 | |
commit | c2cc62d831863151fd0cb7da7ac9a0c324aab871 (patch) | |
tree | 1217bcd4601a77368e948218f85f050cdd647691 /arch/arm64/Kconfig | |
parent | arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context (diff) | |
download | linux-c2cc62d831863151fd0cb7da7ac9a0c324aab871.tar.gz linux-c2cc62d831863151fd0cb7da7ac9a0c324aab871.tar.bz2 linux-c2cc62d831863151fd0cb7da7ac9a0c324aab871.zip |
Now that everything is in place, let's get the ball rolling
by allowing the corresponding config option to be selected.
Also add the required information to silicon_errata.rst.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'arch/arm64/Kconfig')
-rw-r--r-- | arch/arm64/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 950a56b71ff0..b2877ed09307 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -538,6 +538,16 @@ config ARM64_ERRATUM_1286807 invalidated has been observed by other observers. The workaround repeats the TLBI+DSB operation. +config ARM64_ERRATUM_1319367 + bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" + default y + help + This option adds work arounds for ARM Cortex-A57 erratum 1319537 + and A72 erratum 1319367 + + Cortex-A57 and A72 cores could end-up with corrupted TLBs by + speculating an AT instruction during a guest context switch. + If unsure, say Y. config ARM64_ERRATUM_1463225 |