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author | 2023-05-19 19:08:42 +0530 | |
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committer | 2023-06-13 15:08:52 -0700 | |
commit | b59cd2902c58969230a8aca67a10ac3fbde0af15 (patch) | |
tree | 1b31cab2ee887fb8531f52f2a329d8e6a7ba6393 /arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | |
parent | arm64: dts: qcom: sm7225-fairphone-fp4: Add Bluetooth (diff) | |
download | linux-b59cd2902c58969230a8aca67a10ac3fbde0af15.tar.gz linux-b59cd2902c58969230a8aca67a10ac3fbde0af15.tar.bz2 linux-b59cd2902c58969230a8aca67a10ac3fbde0af15.zip |
arm64: dts: qcom: ipq5332: rename mi01.2 dts to rdp441
To align with ipq5332-rdp468.dts, lets rename the mi01.2 dts as well to
ipq5332-rdp441.dts.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230519133844.23512-2-quic_kathirav@quicinc.com
Diffstat (limited to 'arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts')
-rw-r--r-- | arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts new file mode 100644 index 000000000000..3af1d5556950 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 AP-MI01.2 board device tree source + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5332.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; + compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; + + aliases { + serial0 = &blsp1_uart0; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&blsp1_uart0 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&blsp1_i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c_1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhc { + bus-width = <4>; + max-frequency = <192000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board { + clock-frequency = <24000000>; +}; + +/* PINCTRL */ + +&tlmm { + i2c_1_pins: i2c-1-state { + pins = "gpio29", "gpio30"; + function = "blsp1_i2c0"; + drive-strength = <8>; + bias-pull-up; + }; + + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio13"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio12"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; |