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| author |  Thomas Gleixner <tglx@linutronix.de>
| 2023-06-26 11:05:49 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de>
| 2023-06-26 11:05:49 +0200 |
| commit | f121ab7f4ac32ed2aa51035534926f9507a8308b (patch) | |
| tree | d17cd6dc29b64e6d681caa70424f3beacce21f14 /arch/loongarch | |
| parent | genirq: Use a maple tree for interrupt descriptor management (diff) | |
| parent | Merge branch irq/misc-6.5 into irq/irqchip-next (diff) | |
| download | linux-f121ab7f4ac32ed2aa51035534926f9507a8308b.tar.gz linux-f121ab7f4ac32ed2aa51035534926f9507a8308b.tar.bz2 linux-f121ab7f4ac32ed2aa51035534926f9507a8308b.zip | |
Merge tag 'irqchip-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates from Marc Zyngier:
- A number of Loogson/Loogarch fixes
- Allow the core code to retrigger an interrupt that has
fired while the same interrupt is being handled on another
CPU, papering over a GICv3 architecture issue
- Work around an integration problem on ASR8601, where the CPU
numbering isn't representable in the GIC implementation...
- Add some missing interrupt to the STM32 irqchip
- A bunch of warning squashing triggered by W=1 builds
Link: https://lore.kernel.org/r/20230623224345.3577134-1-maz@kernel.org
Diffstat (limited to 'arch/loongarch')
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