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| author |  Bjorn Helgaas <bhelgaas@google.com>
| 2024-01-03 17:16:03 -0600 |
|---|---|---|
| committer |  Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| 2024-01-08 10:39:12 +0100 |
| commit | 2f9060b1db4aa2c21c248e34476d8936a2b69cf6 (patch) | |
| tree | 666738efd029662d2e38b60c3fe3fd398c38376d /arch/mips/include/asm/io.h | |
| parent | MIPS: Remove unused shadow GPR support from vector irq setup (diff) | |
| download | linux-2f9060b1db4aa2c21c248e34476d8936a2b69cf6.tar.gz linux-2f9060b1db4aa2c21c248e34476d8936a2b69cf6.tar.bz2 linux-2f9060b1db4aa2c21c248e34476d8936a2b69cf6.zip | |
MIPS: Fix typos
Fix typos, most reported by "codespell arch/mips". Only touches comments,
no code changes.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-mips@vger.kernel.org
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm/io.h')
| -rw-r--r-- | arch/mips/include/asm/io.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 062dd4e6b954..bba327dc1226 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -179,7 +179,7 @@ void iounmap(const volatile void __iomem *addr); * address is not guaranteed to be usable directly as a virtual * address. * - * This version of ioremap ensures that the memory is marked cachable by + * This version of ioremap ensures that the memory is marked cacheable by * the CPU. Also enables full write-combining. Useful for some * memory-like regions on I/O busses. */ @@ -197,7 +197,7 @@ void iounmap(const volatile void __iomem *addr); * address is not guaranteed to be usable directly as a virtual * address. * - * This version of ioremap ensures that the memory is marked uncachable + * This version of ioremap ensures that the memory is marked uncacheable * but accelerated by means of write-combining feature. It is specifically * useful for PCIe prefetchable windows, which may vastly improve a * communications performance. If it was determined on boot stage, what |