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authorGravatar Justin Swartz <justin.swartz@risingedge.co.za> 2024-03-16 06:54:38 +0200
committerGravatar Thomas Bogendoerfer <tsbogend@alpha.franken.de> 2024-04-15 10:23:37 +0200
commita76a20f9e133dcd70d1cedd2705c58dbee33bb36 (patch)
treeb8f9164e0e90087871ecab43f6f89e30bb2dd1dc /arch/mips
parentmips: dts: ralink: mt7621: reorder mmc node attributes (diff)
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mips: dts: ralink: mt7621: reorder gic node attributes
Reorder the attributes of the Global Interrupt Controller node to fit DTS style guidelines. Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za> Reviewed-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/boot/dts/ralink/mt7621.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi
index 1fbe345bd239..8aa9eba686d5 100644
--- a/arch/mips/boot/dts/ralink/mt7621.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7621.dtsi
@@ -338,15 +338,15 @@
compatible = "mti,gic";
reg = <0x1fbc0000 0x2000>;
- interrupt-controller;
#interrupt-cells = <3>;
+ interrupt-controller;
mti,reserved-cpu-vectors = <7>;
timer {
compatible = "mti,gic-timer";
- interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clocks = <&sysc MT7621_CLK_CPU>;
+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
};
};