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author | 2015-11-17 20:34:51 +0100 | |
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committer | 2015-11-20 12:14:27 +0100 | |
commit | accbfb52d09ac00147f02c4335d1cc47665e6653 (patch) | |
tree | 7a42b6405761c65d3f8b311f294a334e30711aea /arch/mips | |
parent | MIPS: ath79: Fix the DDR control initialization on ar71xx and ar934x (diff) | |
download | linux-accbfb52d09ac00147f02c4335d1cc47665e6653.tar.gz linux-accbfb52d09ac00147f02c4335d1cc47665e6653.tar.bz2 linux-accbfb52d09ac00147f02c4335d1cc47665e6653.zip |
MIPS: ath79: Fix the size of the MISC INTC registers in ar9132.dtsi
There is 2 registers that is 8 bytes long, not 4.
Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Alexander Couzens <lynxis@fe80.eu>
Cc: Joel Porquet <joel@porquet.org>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11508/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/boot/dts/qca/ar9132.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/boot/dts/qca/ar9132.dtsi b/arch/mips/boot/dts/qca/ar9132.dtsi index fb7734eadbf0..13d0439496a9 100644 --- a/arch/mips/boot/dts/qca/ar9132.dtsi +++ b/arch/mips/boot/dts/qca/ar9132.dtsi @@ -107,7 +107,7 @@ miscintc: interrupt-controller@18060010 { compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc"; - reg = <0x18060010 0x4>; + reg = <0x18060010 0x8>; interrupt-parent = <&cpuintc>; interrupts = <6>; |