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authorGravatar Nicholas Piggin <npiggin@gmail.com> 2023-01-21 19:58:03 +1000
committerGravatar Michael Ellerman <mpe@ellerman.id.au> 2023-02-10 22:17:35 +1100
commitfb3b72a3f483f81a33a9693ed03dc62158a6f77e (patch)
tree5f051cc4d21193fbc9dc35ec5848add21d0cce78 /arch/powerpc/include
parentpowerpc/hv-24x7: Fix pvr check when setting interface version (diff)
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powerpc: Consolidate 32-bit and 64-bit interrupt_enter_prepare
There are two separeate implementations for 32-bit and 64-bit which mostly do the same thing. Consolidating on one implementation ends up being smaller and simpler, there is just irq soft-mask reconcile that is specific to 64-bit. There should be no real functional change with this patch, but it does make the context tracking calls necessary for 32-bit to support context tracking. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20230121095805.2823731-2-npiggin@gmail.com
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/interrupt.h35
1 files changed, 8 insertions, 27 deletions
diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/asm/interrupt.h
index 6d8492b6e2b8..a4196ab1d016 100644
--- a/arch/powerpc/include/asm/interrupt.h
+++ b/arch/powerpc/include/asm/interrupt.h
@@ -74,17 +74,18 @@
#include <asm/kprobes.h>
#include <asm/runlatch.h>
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
/*
* WARN/BUG is handled with a program interrupt so minimise checks here to
* avoid recursion and maximise the chance of getting the first oops handled.
*/
#define INT_SOFT_MASK_BUG_ON(regs, cond) \
do { \
- if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG) && \
- (user_mode(regs) || (TRAP(regs) != INTERRUPT_PROGRAM))) \
+ if ((user_mode(regs) || (TRAP(regs) != INTERRUPT_PROGRAM))) \
BUG_ON(cond); \
} while (0)
+#else
+#define INT_SOFT_MASK_BUG_ON(regs, cond)
#endif
#ifdef CONFIG_PPC_BOOK3S_64
@@ -151,28 +152,8 @@ static inline void booke_restore_dbcr0(void)
static inline void interrupt_enter_prepare(struct pt_regs *regs)
{
-#ifdef CONFIG_PPC32
- if (!arch_irq_disabled_regs(regs))
- trace_hardirqs_off();
-
- if (user_mode(regs))
- kuap_lock();
- else
- kuap_save_and_lock(regs);
-
- if (user_mode(regs))
- account_cpu_user_entry();
-#endif
-
#ifdef CONFIG_PPC64
- bool trace_enable = false;
-
- if (IS_ENABLED(CONFIG_TRACE_IRQFLAGS)) {
- if (irq_soft_mask_set_return(IRQS_ALL_DISABLED) == IRQS_ENABLED)
- trace_enable = true;
- } else {
- irq_soft_mask_set(IRQS_ALL_DISABLED);
- }
+ irq_soft_mask_set(IRQS_ALL_DISABLED);
/*
* If the interrupt was taken with HARD_DIS clear, then enable MSR[EE].
@@ -188,9 +169,10 @@ static inline void interrupt_enter_prepare(struct pt_regs *regs)
} else {
__hard_RI_enable();
}
+ /* Enable MSR[RI] early, to support kernel SLB and hash faults */
+#endif
- /* Do this when RI=1 because it can cause SLB faults */
- if (trace_enable)
+ if (!arch_irq_disabled_regs(regs))
trace_hardirqs_off();
if (user_mode(regs)) {
@@ -215,7 +197,6 @@ static inline void interrupt_enter_prepare(struct pt_regs *regs)
}
INT_SOFT_MASK_BUG_ON(regs, !arch_irq_disabled_regs(regs) &&
!(regs->msr & MSR_EE));
-#endif
booke_restore_dbcr0();
}