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authorGravatar Atish Patra <atish.patra@wdc.com> 2022-02-18 16:46:52 -0800
committerGravatar Palmer Dabbelt <palmer@rivosinc.com> 2022-03-21 14:58:12 -0700
commit9dc6ce80213635cdca611d8b89f74bf010c1a8c6 (patch)
treee28bfa5958b09599a37ba62abebb9751bccfeae4 /arch/riscv/Kconfig
parentRISC-V: Improve /proc/cpuinfo output for ISA extensions (diff)
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RISC-V: Remove the current perf implementation
The current perf implementation in RISC-V is not very useful as it can not count any events other than cycle/instructions. Moreover, perf record can not be used or the events can not be started or stopped. Remove the implementation now for a better platform driver in future that will implement most of the missing functionality. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/Kconfig')
-rw-r--r--arch/riscv/Kconfig13
1 files changed, 0 insertions, 13 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 5adcbd9b5e88..00cc3d4c77d1 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -333,19 +333,6 @@ config RISCV_ISA_C
If you don't know what to do here, say Y.
-menu "supported PMU type"
- depends on PERF_EVENTS
-
-config RISCV_BASE_PMU
- bool "Base Performance Monitoring Unit"
- def_bool y
- help
- A base PMU that serves as a reference implementation and has limited
- feature of perf. It can run on any RISC-V machines so serves as the
- fallback, but this option can also be disable to reduce kernel size.
-
-endmenu
-
config FPU
bool "FPU support"
default y