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| author |  Inochi Amaoto <inochiama@outlook.com>
| 2024-03-09 17:02:56 +0800 |
|---|---|---|
| committer | Inochi Amaoto <inochiama@outlook.com>
| 2024-04-11 15:37:50 +0800 |
| commit | 18e8c6d2cced6c57d62813f49b57eeb8ee02f984 (patch) | |
| tree | 5c7ff1e007321d85145591d5758865e28940587b /arch/riscv/boot | |
| parent | riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC (diff) | |
| download | linux-18e8c6d2cced6c57d62813f49b57eeb8ee02f984.tar.gz linux-18e8c6d2cced6c57d62813f49b57eeb8ee02f984.tar.bz2 linux-18e8c6d2cced6c57d62813f49b57eeb8ee02f984.zip | |
riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC
Add missing clocks of uart node for CV1800B and CV1812H.
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/IA1PR20MB4953198222C3ABC2A2B6DE21BB262@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Diffstat (limited to 'arch/riscv/boot')
| -rw-r--r-- | arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index c744c442304c..dc6452a2fe01 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -4,6 +4,7 @@ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> */ +#include <dt-bindings/clock/sophgo,cv1800.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -143,7 +144,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x04140000 0x100>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -153,7 +155,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x04150000 0x100>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -163,7 +166,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x04160000 0x100>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -173,7 +177,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x04170000 0x100>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -183,7 +188,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x041c0000 0x100>; interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; |