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| author |  Andrew Jones <ajones@ventanamicro.com>
| 2022-10-02 10:18:20 +0530 |
|---|---|---|
| committer |  Anup Patel <anup@brainfault.org>
| 2022-10-02 10:18:20 +0530 |
| commit | 26b73f14933e9c0beb88bb2fcee69d93572558ef (patch) | |
| tree | 32269fd6c317898595b40ba3eacdac4001389ec7 /arch/riscv/include | |
| parent | riscv: KVM: Apply insn-def to hfence encodings (diff) | |
| download | linux-26b73f14933e9c0beb88bb2fcee69d93572558ef.tar.gz linux-26b73f14933e9c0beb88bb2fcee69d93572558ef.tar.bz2 linux-26b73f14933e9c0beb88bb2fcee69d93572558ef.zip | |
riscv: KVM: Apply insn-def to hlv encodings
Introduce hlv instruction encodings and apply them to KVM's use.
We're careful not to introduce hlv.d to 32-bit builds. Indeed,
we ensure the build fails if someone tries to use it.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/insn-def.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h index c8aca3c27433..af7b0b55815c 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -97,4 +97,21 @@ INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(49), \ __RD(0), RS1(gaddr), RS2(vmid)) +#define HLVX_HU(dest, addr) \ + INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(50), \ + RD(dest), RS1(addr), __RS2(3)) + +#define HLV_W(dest, addr) \ + INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(52), \ + RD(dest), RS1(addr), __RS2(0)) + +#ifdef CONFIG_64BIT +#define HLV_D(dest, addr) \ + INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(54), \ + RD(dest), RS1(addr), __RS2(0)) +#else +#define HLV_D(dest, addr) \ + __ASM_STR(.error "hlv.d requires 64-bit support") +#endif + #endif /* __ASM_INSN_DEF_H */ |