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| author |  Xiao Wang <xiao.w.wang@intel.com>
| 2023-09-21 22:16:52 +0800 |
|---|---|---|
| committer |  Palmer Dabbelt <palmer@rivosinc.com>
| 2023-10-31 19:15:53 -0700 |
| commit | 92235d3d8365d24f6cc6701b545e764ef144806a (patch) | |
| tree | 4ebcf997b9a3f9f417d804fecbd4b2bd5ed6e094 /arch/riscv/include | |
| parent | RISC-V: clarify the QEMU workaround in ISA parser (diff) | |
| download | linux-92235d3d8365d24f6cc6701b545e764ef144806a.tar.gz linux-92235d3d8365d24f6cc6701b545e764ef144806a.tar.bz2 linux-92235d3d8365d24f6cc6701b545e764ef144806a.zip | |
riscv/mm: Fix the comment for swap pte format
Swap type takes bits 7-11 and swap offset should start from bit 12.
Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Link: https://lore.kernel.org/r/20230921141652.2657054-1-xiao.w.wang@intel.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/pgtable.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index e05e5c8f6526..c8e8867c42f6 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -811,7 +811,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, * bit 5: _PAGE_PROT_NONE (zero) * bit 6: exclusive marker * bits 7 to 11: swap type - * bits 11 to XLEN-1: swap offset + * bits 12 to XLEN-1: swap offset */ #define __SWP_TYPE_SHIFT 7 #define __SWP_TYPE_BITS 5 |