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| author |  Bin Meng <bmeng.cn@gmail.com>
| 2019-08-07 09:13:38 -0700 |
|---|---|---|
| committer |  Paul Walmsley <paul.walmsley@sifive.com>
| 2019-08-30 11:04:19 -0700 |
| commit | 4f3f90084673fa1d7f8e81b9dbee652d2fae3092 (patch) | |
| tree | a5abbf3544fa42ac8002295f45abaa4f70e2120f /arch/riscv/kernel/head.S | |
| parent | Merge tag 'common/for-v5.4-rc1/cpu-topology' into for-v5.4-rc1-branch (diff) | |
| download | linux-4f3f90084673fa1d7f8e81b9dbee652d2fae3092.tar.gz linux-4f3f90084673fa1d7f8e81b9dbee652d2fae3092.tar.bz2 linux-4f3f90084673fa1d7f8e81b9dbee652d2fae3092.zip | |
riscv: Using CSR numbers to access CSRs
Since commit a3182c91ef4e ("RISC-V: Access CSRs using CSR numbers"),
we should prefer accessing CSRs using their CSR numbers, but there
are several leftovers like sstatus / sptbr we missed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'arch/riscv/kernel/head.S')
| -rw-r--r-- | arch/riscv/kernel/head.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 0f1ba17e476f..86049aed8251 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -61,7 +61,7 @@ _start_kernel: * floating point in kernel space */ li t0, SR_FS - csrc sstatus, t0 + csrc CSR_SSTATUS, t0 /* Pick one hart to run the main boot sequence */ la a3, hart_lottery |