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author | Atish Patra <atishp@rivosinc.com> | 2023-02-07 01:55:22 -0800 |
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committer | Anup Patel <anup@brainfault.org> | 2023-02-07 20:35:51 +0530 |
commit | 8f0153ecd3bf184bc06afca25b737c707fa4d765 (patch) | |
tree | 05d97577625e023d709eca63fb8d8de5184e5256 /arch/riscv/kernel/mcount.S | |
parent | RISC-V: KVM: Modify SBI extension handler to return SBI error code (diff) | |
download | linux-8f0153ecd3bf184bc06afca25b737c707fa4d765.tar.gz linux-8f0153ecd3bf184bc06afca25b737c707fa4d765.tar.bz2 linux-8f0153ecd3bf184bc06afca25b737c707fa4d765.zip |
RISC-V: KVM: Add skeleton support for perf
This patch only adds barebone structure of perf implementation. Most
of the function returns zero at this point and will be implemented
fully in the future.
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/kernel/mcount.S')
0 files changed, 0 insertions, 0 deletions