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| author |  Clément Léger <cleger@rivosinc.com>
| 2023-10-04 17:14:00 +0200 |
|---|---|---|
| committer |  Palmer Dabbelt <palmer@rivosinc.com>
| 2023-11-01 08:34:54 -0700 |
| commit | 89c12fecdc4d46c1f08a81dab5d305304cc626eb (patch) | |
| tree | 068e35d054b3aef9078ee2ba7ae76d8061c847ce /arch/riscv/kernel | |
| parent | riscv: add support for misaligned trap handling in S-mode (diff) | |
| download | linux-89c12fecdc4d46c1f08a81dab5d305304cc626eb.tar.gz linux-89c12fecdc4d46c1f08a81dab5d305304cc626eb.tar.bz2 linux-89c12fecdc4d46c1f08a81dab5d305304cc626eb.zip | |
riscv: report perf event for misaligned fault
Add missing calls to account for misaligned fault event using
perf_sw_event().
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Link: https://lore.kernel.org/r/20231004151405.521596-4-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/kernel')
| -rw-r--r-- | arch/riscv/kernel/traps_misaligned.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 9daed7d756ae..804f6c5e0e44 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -6,6 +6,7 @@ #include <linux/init.h> #include <linux/mm.h> #include <linux/module.h> +#include <linux/perf_event.h> #include <linux/irq.h> #include <linux/stringify.h> @@ -294,6 +295,8 @@ int handle_misaligned_load(struct pt_regs *regs) unsigned long addr = regs->badaddr; int i, fp = 0, shift = 0, len = 0; + perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + if (get_insn(regs, epc, &insn)) return -1; @@ -382,6 +385,8 @@ int handle_misaligned_store(struct pt_regs *regs) unsigned long addr = regs->badaddr; int i, len = 0; + perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + if (get_insn(regs, epc, &insn)) return -1; |