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| author |  Mayuresh Chitale <mchitale@ventanamicro.com>
| 2023-09-13 22:09:04 +0530 |
|---|---|---|
| committer |  Anup Patel <anup@brainfault.org>
| 2023-10-12 18:44:11 +0530 |
| commit | 81f0f314fec92a69d6c4951b9d9db21d37419669 (patch) | |
| tree | e81ee64f7c2ab6a212e0af29a82cd8bbbac08cc8 /arch/riscv/kvm/vcpu.c | |
| parent | RISCV: KVM: Add senvcfg context save/restore (diff) | |
| download | linux-81f0f314fec92a69d6c4951b9d9db21d37419669.tar.gz linux-81f0f314fec92a69d6c4951b9d9db21d37419669.tar.bz2 linux-81f0f314fec92a69d6c4951b9d9db21d37419669.zip | |
RISCV: KVM: Add sstateen0 context save/restore
Define sstateen0 and add sstateen0 save/restore for guest VCPUs.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/kvm/vcpu.c')
| -rw-r--r-- | arch/riscv/kvm/vcpu.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 3013ae30c3af..c061a1c5fe98 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -621,16 +621,28 @@ static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu) static __always_inline void kvm_riscv_vcpu_swap_in_guest_state(struct kvm_vcpu *vcpu) { + struct kvm_vcpu_smstateen_csr *smcsr = &vcpu->arch.smstateen_csr; struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; + struct kvm_vcpu_config *cfg = &vcpu->arch.cfg; vcpu->arch.host_senvcfg = csr_swap(CSR_SENVCFG, csr->senvcfg); + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) && + (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0)) + vcpu->arch.host_sstateen0 = csr_swap(CSR_SSTATEEN0, + smcsr->sstateen0); } static __always_inline void kvm_riscv_vcpu_swap_in_host_state(struct kvm_vcpu *vcpu) { + struct kvm_vcpu_smstateen_csr *smcsr = &vcpu->arch.smstateen_csr; struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; + struct kvm_vcpu_config *cfg = &vcpu->arch.cfg; csr->senvcfg = csr_swap(CSR_SENVCFG, vcpu->arch.host_senvcfg); + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) && + (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0)) + smcsr->sstateen0 = csr_swap(CSR_SSTATEEN0, + vcpu->arch.host_sstateen0); } /* |