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| author |  Anup Patel <apatel@ventanamicro.com>
| 2022-10-21 11:52:45 +0530 |
|---|---|---|
| committer |  Anup Patel <anup@brainfault.org>
| 2022-10-21 11:52:45 +0530 |
| commit | cea8896bd936135559253e9b23340cfa1cdf0caf (patch) | |
| tree | a5c94163df10e7c56cab18976231642efd44efa2 /arch/riscv/kvm/vcpu.c | |
| parent | RISC-V: Fix compilation without RISCV_ISA_ZICBOM (diff) | |
| download | linux-cea8896bd936135559253e9b23340cfa1cdf0caf.tar.gz linux-cea8896bd936135559253e9b23340cfa1cdf0caf.tar.bz2 linux-cea8896bd936135559253e9b23340cfa1cdf0caf.zip | |
RISC-V: KVM: Fix kvm_riscv_vcpu_timer_pending() for Sstc
The kvm_riscv_vcpu_timer_pending() checks per-VCPU next_cycles
and per-VCPU software injected VS timer interrupt. This function
returns incorrect value when Sstc is available because the per-VCPU
next_cycles are only updated by kvm_riscv_vcpu_timer_save() called
from kvm_arch_vcpu_put(). As a result, when Sstc is available the
VCPU does not block properly upon WFI traps.
To fix the above issue, we introduce kvm_riscv_vcpu_timer_sync()
which will update per-VCPU next_cycles upon every VM exit instead
of kvm_riscv_vcpu_timer_save().
Fixes: 8f5cb44b1bae ("RISC-V: KVM: Support sstc extension")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/kvm/vcpu.c')
| -rw-r--r-- | arch/riscv/kvm/vcpu.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index a032c4f0d600..71ebbc4821f0 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -708,6 +708,9 @@ void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu) clear_bit(IRQ_VS_SOFT, &v->irqs_pending); } } + + /* Sync-up timer CSRs */ + kvm_riscv_vcpu_timer_sync(vcpu); } int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) |