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| author |  Michael Roth <michael.roth@amd.com>
| 2022-02-24 10:56:12 -0600 |
|---|---|---|
| committer |  Borislav Petkov <bp@suse.de>
| 2022-04-07 16:47:11 +0200 |
| commit | ee0bfa08a345370df28c07288e886abcbaac481f (patch) | |
| tree | 671581997cc19cd6d43041c12fb3713de66976e0 /arch/x86/include/asm/sev-common.h | |
| parent | x86/sev: Move MSR-based VMGEXITs for CPUID to helper (diff) | |
| download | linux-ee0bfa08a345370df28c07288e886abcbaac481f.tar.gz linux-ee0bfa08a345370df28c07288e886abcbaac481f.tar.bz2 linux-ee0bfa08a345370df28c07288e886abcbaac481f.zip | |
x86/compressed/64: Add support for SEV-SNP CPUID table in #VC handlers
CPUID instructions generate a #VC exception for SEV-ES/SEV-SNP guests,
for which early handlers are currently set up to handle. In the case
of SEV-SNP, guests can use a configurable location in guest memory
that has been pre-populated with a firmware-validated CPUID table to
look up the relevant CPUID values rather than requesting them from
hypervisor via a VMGEXIT. Add the various hooks in the #VC handlers to
allow CPUID instructions to be handled via the table. The code to
actually configure/enable the table will be added in a subsequent
commit.
Signed-off-by: Michael Roth <michael.roth@amd.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20220307213356.2797205-33-brijesh.singh@amd.com
Diffstat (limited to 'arch/x86/include/asm/sev-common.h')
| -rw-r--r-- | arch/x86/include/asm/sev-common.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index e9b6815b3b3d..0759af9b1acf 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -152,6 +152,8 @@ struct snp_psc_desc { #define GHCB_TERM_PSC 1 /* Page State Change failure */ #define GHCB_TERM_PVALIDATE 2 /* Pvalidate failure */ #define GHCB_TERM_NOT_VMPL0 3 /* SNP guest is not running at VMPL-0 */ +#define GHCB_TERM_CPUID 4 /* CPUID-validation failure */ +#define GHCB_TERM_CPUID_HV 5 /* CPUID failure during hypervisor fallback */ #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) |