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| author |  Sean Christopherson <seanjc@google.com>
| 2024-01-09 16:23:40 -0800 |
|---|---|---|
| committer | Sean Christopherson <seanjc@google.com>
| 2024-02-22 16:03:56 -0800 |
| commit | b1a3c366cbc783d6600b357ccfec2f440eed5453 (patch) | |
| tree | 8d39c1014c757db8ed2aebcff1f8cc23c8ab6c98 /arch/x86/kernel/cpu/feat_ctl.c | |
| parent | KVM: VMX: Report up-to-date exit qualification to userspace (diff) | |
| download | linux-b1a3c366cbc783d6600b357ccfec2f440eed5453.tar.gz linux-b1a3c366cbc783d6600b357ccfec2f440eed5453.tar.bz2 linux-b1a3c366cbc783d6600b357ccfec2f440eed5453.zip | |
x86/cpu: Add a VMX flag to enumerate 5-level EPT support to userspace
Add a VMX flag in /proc/cpuinfo, ept_5level, so that userspace can query
whether or not the CPU supports 5-level EPT paging. EPT capabilities are
enumerated via MSR, i.e. aren't accessible to userspace without help from
the kernel, and knowing whether or not 5-level EPT is supported is useful
for debug, triage, testing, etc.
For example, when EPT is enabled, bits 51:48 of guest physical addresses
are consumed by the CPU if and only if 5-level EPT is enabled. For CPUs
with MAXPHYADDR > 48, KVM *can't* map all legal guest memory without
5-level EPT, making 5-level EPT support valuable information for userspace.
Reported-by: Yi Lai <yi1.lai@intel.com>
Cc: Tao Su <tao1.su@linux.intel.com>
Cc: Xudong Hao <xudong.hao@intel.com>
Link: https://lore.kernel.org/r/20240110002340.485595-1-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
Diffstat (limited to 'arch/x86/kernel/cpu/feat_ctl.c')
| -rw-r--r-- | arch/x86/kernel/cpu/feat_ctl.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/feat_ctl.c b/arch/x86/kernel/cpu/feat_ctl.c index 03851240c3e3..1640ae76548f 100644 --- a/arch/x86/kernel/cpu/feat_ctl.c +++ b/arch/x86/kernel/cpu/feat_ctl.c @@ -72,6 +72,8 @@ static void init_vmx_capabilities(struct cpuinfo_x86 *c) c->vmx_capability[MISC_FEATURES] |= VMX_F(EPT_AD); if (ept & VMX_EPT_1GB_PAGE_BIT) c->vmx_capability[MISC_FEATURES] |= VMX_F(EPT_1GB); + if (ept & VMX_EPT_PAGE_WALK_5_BIT) + c->vmx_capability[MISC_FEATURES] |= VMX_F(EPT_5LEVEL); /* Synthetic APIC features that are aggregates of multiple features. */ if ((c->vmx_capability[PRIMARY_CTLS] & VMX_F(VIRTUAL_TPR)) && |