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author | H. Peter Anvin (Intel) <hpa@zytor.com> | 2023-12-05 02:50:07 -0800 |
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committer | Borislav Petkov (AMD) <bp@alien8.de> | 2024-01-31 22:01:41 +0100 |
commit | 09794f68936a017e5632774c3e4450bebbcca2cb (patch) | |
tree | 6278e66e36bda60871c44d38c5b75fd350683c39 /arch/x86/kernel/espfix_64.c | |
parent | x86/fred: Update MSR_IA32_FRED_RSP0 during task switch (diff) | |
download | linux-09794f68936a017e5632774c3e4450bebbcca2cb.tar.gz linux-09794f68936a017e5632774c3e4450bebbcca2cb.tar.bz2 linux-09794f68936a017e5632774c3e4450bebbcca2cb.zip |
x86/fred: Disallow the swapgs instruction when FRED is enabled
SWAPGS is no longer needed thus NOT allowed with FRED because FRED
transitions ensure that an operating system can _always_ operate
with its own GS base address:
- For events that occur in ring 3, FRED event delivery swaps the GS
base address with the IA32_KERNEL_GS_BASE MSR.
- ERETU (the FRED transition that returns to ring 3) also swaps the
GS base address with the IA32_KERNEL_GS_BASE MSR.
And the operating system can still setup the GS segment for a user
thread without the need of loading a user thread GS with:
- Using LKGS, available with FRED, to modify other attributes of the
GS segment without compromising its ability always to operate with
its own GS base address.
- Accessing the GS segment base address for a user thread as before
using RDMSR or WRMSR on the IA32_KERNEL_GS_BASE MSR.
Note, LKGS loads the GS base address into the IA32_KERNEL_GS_BASE MSR
instead of the GS segment's descriptor cache. As such, the operating
system never changes its runtime GS base address.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Tested-by: Shan Kang <shan.kang@intel.com>
Link: https://lore.kernel.org/r/20231205105030.8698-19-xin3.li@intel.com
Diffstat (limited to 'arch/x86/kernel/espfix_64.c')
0 files changed, 0 insertions, 0 deletions