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authorGravatar Thomas Gleixner <tglx@linutronix.de> 2023-10-17 23:23:26 +0200
committerGravatar Borislav Petkov (AMD) <bp@alien8.de> 2023-10-18 18:27:30 +0200
commita62f4ca106fd250e9247decd100f3905131fc1fe (patch)
treeca6390e5e813052afce2fdaa0e49c654ef47dd8b /arch/x86/kernel/head32.c
parentx86/boot: Use __pa_nodebug() in mk_early_pgtbl_32() (diff)
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x86/boot/32: De-uglify the 2/3 level paging difference in mk_early_pgtbl_32()
Move the ifdeffery out of the function and use proper typedefs to make it work for both 2 and 3 level paging. No functional change. [ bp: Move mk_early_pgtbl_32() declaration into a header. ] Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20231017211722.111059491@linutronix.de
Diffstat (limited to 'arch/x86/kernel/head32.c')
-rw-r--r--arch/x86/kernel/head32.c38
1 files changed, 20 insertions, 18 deletions
diff --git a/arch/x86/kernel/head32.c b/arch/x86/kernel/head32.c
index 8fe0dd38fff0..2b6599807026 100644
--- a/arch/x86/kernel/head32.c
+++ b/arch/x86/kernel/head32.c
@@ -69,41 +69,43 @@ asmlinkage __visible void __init __noreturn i386_start_kernel(void)
* to the first kernel PMD. Note the upper half of each PMD or PTE are
* always zero at this stage.
*/
-void __init mk_early_pgtbl_32(void);
+#ifdef CONFIG_X86_PAE
+typedef pmd_t pl2_t;
+#define pl2_base initial_pg_pmd
+#define SET_PL2(val) { .pmd = (val), }
+#else
+typedef pgd_t pl2_t;
+#define pl2_base initial_page_table
+#define SET_PL2(val) { .pgd = (val), }
+#endif
void __init __no_stack_protector mk_early_pgtbl_32(void)
{
- pte_t pte, *ptep;
- int i;
- unsigned long *ptr;
/* Enough space to fit pagetables for the low memory linear map */
const unsigned long limit = __pa_nodebug(_end) +
(PAGE_TABLE_SIZE(LOWMEM_PAGES) << PAGE_SHIFT);
-#ifdef CONFIG_X86_PAE
- pmd_t pl2, *pl2p = (pmd_t *)__pa_nodebug(initial_pg_pmd);
-#define SET_PL2(pl2, val) { (pl2).pmd = (val); }
-#else
- pgd_t pl2, *pl2p = (pgd_t *)__pa_nodebug(initial_page_table);
-#define SET_PL2(pl2, val) { (pl2).pgd = (val); }
-#endif
+ pte_t pte, *ptep = (pte_t *)__pa_nodebug(__brk_base);
+ pl2_t *pl2p = (pl2_t *)__pa_nodebug(pl2_base);
+ unsigned long *ptr;
+ int i;
- ptep = (pte_t *)__pa_nodebug(__brk_base);
pte.pte = PTE_IDENT_ATTR;
while ((pte.pte & PTE_PFN_MASK) < limit) {
+ pl2_t pl2 = SET_PL2((unsigned long)ptep | PDE_IDENT_ATTR);
- SET_PL2(pl2, (unsigned long)ptep | PDE_IDENT_ATTR);
*pl2p = pl2;
-#ifndef CONFIG_X86_PAE
- /* Kernel PDE entry */
- *(pl2p + ((PAGE_OFFSET >> PGDIR_SHIFT))) = pl2;
-#endif
+
+ if (!IS_ENABLED(CONFIG_X86_PAE)) {
+ /* Kernel PDE entry */
+ *(pl2p + ((PAGE_OFFSET >> PGDIR_SHIFT))) = pl2;
+ }
+
for (i = 0; i < PTRS_PER_PTE; i++) {
*ptep = pte;
pte.pte += PAGE_SIZE;
ptep++;
}
-
pl2p++;
}