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| author |  Sean Christopherson <seanjc@google.com>
| 2023-01-24 23:49:00 +0000 |
|---|---|---|
| committer | Sean Christopherson <seanjc@google.com>
| 2023-01-26 18:03:42 -0800 |
| commit | 8911ce66697e04ce7e92753dbf5645f748e27e12 (patch) | |
| tree | e34fece68393ccf1c987390adc3d9488c7dfe4f8 /arch/x86/kvm/vmx/pmu_intel.c | |
| parent | KVM: x86/pmu: Drop event_type and rename "struct kvm_event_hw_type_mapping" (diff) | |
| download | linux-8911ce66697e04ce7e92753dbf5645f748e27e12.tar.gz linux-8911ce66697e04ce7e92753dbf5645f748e27e12.tar.bz2 linux-8911ce66697e04ce7e92753dbf5645f748e27e12.zip | |
KVM: x86/pmu: Cap kvm_pmu_cap.num_counters_gp at KVM's internal max
Limit kvm_pmu_cap.num_counters_gp during kvm_init_pmu_capability() based
on the vendor PMU capabilities so that consuming num_counters_gp naturally
does the right thing. This fixes a mostly theoretical bug where KVM could
over-report its PMU support in KVM_GET_SUPPORTED_CPUID for leaf 0xA, e.g.
if the number of counters reported by perf is greater than KVM's
hardcoded internal limit. Incorporating input from the AMD PMU also
avoids over-reporting MSRs to save when running on AMD.
Link: https://lore.kernel.org/r/20230124234905.3774678-2-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
Diffstat (limited to 'arch/x86/kvm/vmx/pmu_intel.c')
| -rw-r--r-- | arch/x86/kvm/vmx/pmu_intel.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index ef24d254cf06..e8a3be0b9df9 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -815,4 +815,5 @@ struct kvm_pmu_ops intel_pmu_ops __initdata = { .deliver_pmi = intel_pmu_deliver_pmi, .cleanup = intel_pmu_cleanup, .EVENTSEL_EVENT = ARCH_PERFMON_EVENTSEL_EVENT, + .MAX_NR_GP_COUNTERS = KVM_INTEL_PMC_MAX_GENERIC, }; |