diff options
author | 2015-10-16 17:01:04 +0300 | |
---|---|---|
committer | 2015-11-03 17:19:38 +0300 | |
commit | ab45fb145096799dabd18afc58bb5f97171017cd (patch) | |
tree | c2aacf7f7c4a8961a239cb4ee215610b3eeb0d51 /arch/xtensa/include | |
parent | xtensa: add FORCE_MAX_ZONEORDER to Kconfig (diff) | |
download | linux-ab45fb145096799dabd18afc58bb5f97171017cd.tar.gz linux-ab45fb145096799dabd18afc58bb5f97171017cd.tar.bz2 linux-ab45fb145096799dabd18afc58bb5f97171017cd.zip |
xtensa: fix secondary core boot in SMP
There are multiple factors adding to the issue in different
configurations:
- commit 17290231df16eeee ("xtensa: add fixup for double exception raised
in window overflow") added function window_overflow_restore_a0_fixup to
double exception vector overlapping reset vector location of secondary
processor cores.
- on MMUv2 cores RESET_VECTOR1_VADDR may point to uncached kernel memory
making code overlapping depend on cache type and size, so that without
cache or with WT cache reset vector code overwrites double exception
code, making issue even harder to detect.
- on MMUv3 cores RESET_VECTOR1_VADDR may point to unmapped area, as
MMUv3 cores change virtual address map to match MMUv2 layout, but
reset vector virtual address is given for the original MMUv3 mapping.
- physical memory region of the secondary reset vector is not reserved
in the physical memory map, and thus may be allocated and overwritten
at arbitrary moment.
Fix it as follows:
- move window_overflow_restore_a0_fixup code to .text section.
- define RESET_VECTOR1_VADDR so that it points to reset vector in the
cacheable MMUv2 map for cores with MMU.
- reserve reset vector region in the physical memory map. Drop separate
literal section and build mxhead.S with text section literals.
Cc: <stable@vger.kernel.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/include')
-rw-r--r-- | arch/xtensa/include/asm/vectors.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/xtensa/include/asm/vectors.h b/arch/xtensa/include/asm/vectors.h index e34eaecc9f3d..d3e6d2eff783 100644 --- a/arch/xtensa/include/asm/vectors.h +++ b/arch/xtensa/include/asm/vectors.h @@ -61,6 +61,9 @@ static inline unsigned long xtensa_get_kio_paddr(void) #define LOAD_MEMORY_ADDRESS 0xD0003000 #endif +#define RESET_VECTOR1_VADDR (VIRTUAL_MEMORY_ADDRESS + \ + XCHAL_RESET_VECTOR1_PADDR) + #else /* !defined(CONFIG_MMU) */ /* MMU Not being used - Virtual == Physical */ @@ -73,6 +76,8 @@ static inline unsigned long xtensa_get_kio_paddr(void) /* Loaded just above possibly live vectors */ #define LOAD_MEMORY_ADDRESS (PLATFORM_DEFAULT_MEM_START + 0x3000) +#define RESET_VECTOR1_VADDR (XCHAL_RESET_VECTOR1_VADDR) + #endif /* CONFIG_MMU */ #define XC_VADDR(offset) (VIRTUAL_MEMORY_ADDRESS + offset) @@ -84,10 +89,6 @@ static inline unsigned long xtensa_get_kio_paddr(void) VECBASE_RESET_VADDR) #define RESET_VECTOR_VADDR XC_VADDR(RESET_VECTOR_VECOFS) -#define RESET_VECTOR1_VECOFS (XCHAL_RESET_VECTOR1_VADDR - \ - VECBASE_RESET_VADDR) -#define RESET_VECTOR1_VADDR XC_VADDR(RESET_VECTOR1_VECOFS) - #if defined(XCHAL_HAVE_VECBASE) && XCHAL_HAVE_VECBASE #define USER_VECTOR_VADDR XC_VADDR(XCHAL_USER_VECOFS) |